Datasheet NE570 (ON Semiconductor) - 3

NE570 CIRCUIT DESCRIPTION
distortion. The only distortion which remains is even The NE570 compandor building blocks, as shown in the harmonics, and they exist only because of internal offset block diagram, are a full−wave rectifier, a variable gain cell, voltages. The THD trim terminal provides a means for an operational amplifier and a bias system. The arrangement nulling the internal offsets for low distortion operation. of these blocks in the IC result in a circuit which can perform The operational amplifier (which is internally well with few external components, yet can be adapted to compensated) has the non−inverting input tied to VREF, and many diverse applications. the inverting input connected to the DG cell output as well The full−wave rectifier rectifies the input current which as brought out externally. A resistor, R3, is brought out from flows from the rectifier input, to an internal summing node the summing node and allows compressor or expander gain which is biased at VREF. The rectified current is averaged on to be determined only by internal components. an external filter capacitor tied to the CRECT terminal, and The output stage is capable of ±20 mA output current. the average value of the input current controls the gain of the This allows a +13 dBm (3.5 VRMS) output into a 300 W load variable gain cell. The gain will thus be proportional to the which, with a series resistor and proper transformer, can average value of the input signal for capacitively−coupled result in +13 dBm with a 600 W output impedance. voltage inputs as shown in the following equation. Note that A bandgap reference provides the reference voltage for all for capacitively−coupled inputs there is no offset voltage summing nodes, a regulated supply voltage for the rectifier capable of producing a gain error. The only error will come and DG cell, and a bias current for the DG cell. The low from the bias current of the rectifier (supplied internally) tempco of this type of reference provides very stable biasing which is less than 0.1 mA. over a wide temperature range. |V * V | avg The typical performance characteristics illustration G T IN REF R shows the basic input−output transfer curve for basic 1 compressor or expander circuits. or | V | avg G T IN R (dBm) 1 The speed with which gain changes to follow changes in +20 LEVEL input signal levels is determined by the rectifier filter +10 capacitor. A small capacitor will yield rapid response but 0 will not fully filter low frequency signals. Any ripple on the OUTPUT gain control signal will modulate the signal passing through −10 the variable gain cell. In an expander or compressor −20 application, this would lead to third harmonic distortion, so ANDOR there is a trade−off to be made between fast attack and decay −30 times and distortion. For step changes in amplitude, the OR EXP −40 change in gain with time is shown by this equation. *t −50 G(t) + (G * G ) e t ) G initial final final LEVEL −60 t + 10kW CRECT INPUT −70 The variable gain cell is a current−in, current−out device with the ratio I −80 OUT/IIN controlled by the rectifier. IIN is the current which flows from the DG input to an internal −40 −30 −20 −10 0 +10 summing node biased at VREF. The following equation COMPRESSOR OUTPUT LEVEL applies for capacitively−coupled inputs. The output current, OR COMPRESSOR EXPANDOR INPUT LEVEL (dBm) IOUT, is fed to the summing node of the op amp. V * V V I + IN REF + IN
Figure 2. Basic Input−Output Transfer Curve
IN R R 2 2 A compensation scheme built into the DG cell compensates for temperature and cancels out odd harmonic
http://onsemi.com 3