Datasheet STA8610A (STMicroelectronics) - 3

制造商STMicroelectronics
描述Automotive TeseoVI+ Quad-bands GNSS Receiver
页数 / 页7 / 3 — STA8610A. Introduction. 1.1. Description. 1.2. Block diagram. Figure 1. …
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STA8610A. Introduction. 1.1. Description. 1.2. Block diagram. Figure 1. Block diagram. GNSS. Ant sensing. System. Interfaces. Dual core

STA8610A Introduction 1.1 Description 1.2 Block diagram Figure 1 Block diagram GNSS Ant sensing System Interfaces Dual core

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STA8610A Introduction 1 Introduction 1.1 Description
The STA8610A is a quad-band multiconstellation positioning receiver IC. It supports multiband constellations up to quad-band with a single die approach. It includes a dual-processor architecture that gives enough resources for supporting the RTK/PPP precision algorithms on chip. Thanks to the software development kit (SDK), the STA8610A is an ideal open platform to be augmented with high-value sofware features such as RTK/PPP, and precise heading. The dual-antenna architecture is also supported thanks to the IQ interface to be connected with the external STA5635A RF IC. It is the ideal platform for supporting antispoofing and precise heading algorithms. The STA8610AS1 also includes a hardware security module (HSM) to support secure boot. This module, with the signal and interface integrity mechanism, makes the STA8610A the ideal solution for applications where integrity is a key factor. The STA8610A supports a highly evolved antijamming and antispoofing mechanism to mitigate attacks thanks to independent L5 acquisition and tracking, and to the Galileo OSNMA capability. The innovative RF architecture and GNSS baseband make it ready to support new emerging low Earth orbit (LEO) constellations. It is compliant with the ST automotive-grade qualification, which is included in addition to the AEC-Q100 requirements. The usage of in-house manufacturing fabrication plants combined with a set of production flow methodologies targeting zero defect per million, makes the STA8610A the ideal solution for stringent automotive quality and supply chain requirements. The device is delivered in a BGA package. Note: For information on the Arm® core, refer to the Arm® Cortex®‑M7 technical reference manual, available from the www.arm.com website. Note: Arm, Cortex, and the Arm logo are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
1.2 Block diagram Figure 1. Block diagram GNSS Ant sensing System Interfaces
G6RF G6BB 10-bit ADC ×2 Interrupt ctrl DMA EFT UART ×3 Watchdog JTAG SSP ×2
Dual core GNSS engines Always on domain
I²C Arm® Cortex®-M7 eRAM IQ port 32 kHz oscillator RTC positioning engine Cache SPIQ Power, reset, and clock controller Arm® Cortex®-M7 PPS ×2 measurement engine eNVM (PRCC) Trigger input ×2
Security/integrity PMU
LDOs ×4 LDO backup Hardware security On-the-fly
EMI
module (HSM) decryptor Bandgap, bias, LVDS Octo-SPI
DB5485
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Rev 1 page 3/7
Document Outline STA8610A Features 1 Introduction 1.1 Description 1.2 Block diagram Revision history Glossary ADC AEC ASIL BeiDou CBC CDM DMA DRAW DRUM ESD Galileo GLONASS GNSS GPIO GPS HBM HSM HSSTP IRNSS ISO I²C JTAG LDO LEO LVDS MIPS NAVIC NVM OSNMA P2P PCB PPP PPS PVT QFN QZSS RAM RTK SBAS SDK SPI SPIQ SSP ST UART