Datasheet FL7921R (ON Semiconductor) - 4

FL7921R PIN CONFIGURATION
RANGE 1 16 HV COMP 2 15 NC INV 3 14 ZCD CSPFC 4 13 VIN CSPWM 5 12 RT OPFC 6 11 FB VDD 7 10 DET OPWM 8 9 GND
Figure 3. Pin Configuration PIN DEFINITIONS Pin # Name Description
1 RANGE RANGE pin’s impedance changes according to the VIN pin voltage level. When the input voltage detected by the VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage is at a high level. 2 COMP Output pin of the error amplifier. It’s a Trans−conductance−type error amplifier for PFC output voltage feedback. Proprietary multi−vector current is built−in to this amplifier. Therefore, the compensation for PFC voltage feedback loop allows a simple compensation circuit between this pin and GND. 3 INV Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage divider and provides PFC output over− and under−voltage protections. 4 CSPFC Input to the PFC over−current protection comparator that provides cycle−by−cycle current limiting protection. When the sensed voltage across the PFC current−sensing resistor reaches the internal threshold (0.82 V typical), the PFC switch is turned off to activate cycle−by−cycle current limiting. 5 CSPWM Input to the comparator of the PWM over−current protection and performs PWM current−mode control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch and the sensing voltage is applied to the CSPWM pin for the cycle−by−cycle current limit, current− mode control, and high / low line over−power compensation according to the DET pin source current during PWM tON time. 6 OPFC Totem−pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5 V. 7 VDD Power supply. The threshold voltages for startup and turn−off are 18 V and 7.5 V, respectively. The startup current is less than 30 mA and the operating current is lower than 10 mA. 8 OPWM Totem−pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5 V. 9 GND The power ground and signal ground. 10 DET This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes: Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over−power compensation. The offset is generated in accordance with the input voltage when the PWM switch is on. Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching and minimize the switching loss on the PWM switch. Providing output over−voltage protection. A voltage comparator is built−in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than 2.5 V, the controller enters auto recovery mode. 11 FB Feedback voltage pin. This pin is used to receive the output voltage / current level signal to determine PWM gate duty for regulating output voltage / current. The FB pin voltage can also activate open−loop, overload, and output−short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for more than 50 ms. The input impedance of this pin is a 5 kW equivalent resistance. A one−third attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
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