Datasheet HEF4013B (Nexperia) - 8
| 制造商 | Nexperia |
| 描述 | Dual D-Type Flip-Flop |
| 页数 / 页 | 14 / 8 — Nexperia. HEF4013B. Dual D-type flip-flop. Fig. 4. nSD, nCD recovery time … |
| 文件格式/大小 | PDF / 253 Kb |
| 文件语言 | 英语 |
Nexperia. HEF4013B. Dual D-type flip-flop. Fig. 4. nSD, nCD recovery time and pulse width. Table 9. Measurement points
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Nexperia HEF4013B Dual D-type flip-flop
VI input nCP VM 0 V trec trec VI input nSD VM 0 V tW VI input nCD VM 0 V tW VOH output nQ 001aag088 VOL Recovery times are shown as positive values but may be specified as negative values. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9.
Fig. 4. nSD, nCD recovery time and pulse width Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VDD VI VO G DUT C R L T 001aag182 Test and measurement data is given in Table 10; Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance.
Fig. 5. Test circuit for measuring switching times Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. Al rights reserved
Product data sheet Rev. 12 — 24 July 2024 8 / 14
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents
Nexperia HEF4013B Dual D-type flip-flop
VI input nCP VM 0 V trec trec VI input nSD VM 0 V tW VI input nCD VM 0 V tW VOH output nQ 001aag088 VOL Recovery times are shown as positive values but may be specified as negative values. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9.
Fig. 4. nSD, nCD recovery time and pulse width Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VDD VI VO G DUT C R L T 001aag182 Test and measurement data is given in Table 10; Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance.
Fig. 5. Test circuit for measuring switching times Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. Al rights reserved
Product data sheet Rev. 12 — 24 July 2024 8 / 14
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents