Datasheet OPA206, OPA2206, OPA4206 (Texas Instruments) - 7
| 制造商 | Texas Instruments |
| 描述 | Input-overvoltage-protected, low-power, low-noise four-channel op amp with super-beta inputs |
| 页数 / 页 | 48 / 7 — OPA206. , OPA2206. , OPA4206. www.ti.com. 5.7 Electrical Characteristics: … |
| 文件格式/大小 | PDF / 3.3 Mb |
| 文件语言 | 英语 |
OPA206. , OPA2206. , OPA4206. www.ti.com. 5.7 Electrical Characteristics: VS = ±5 V. PARAMETER. TEST CONDITIONS. MIN. TYP. MAX. UNIT
该数据表的模型线
文件文字版本
OPA206 , OPA2206 , OPA4206 www.ti.com
SBOSA11E – MARCH 2020 – REVISED DECEMBER 2023
5.7 Electrical Characteristics: VS = ±5 V
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE
±4 ±25 VOS Input offset voltage μV TA = –40°C to +125°C ±55 dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±0.08 ±0.5 μV/°C Power supply rejection ±0.05 ±0.5 PSRR V μV/V ratio S = ±2.25 V to ±18 V TA = –40°C to +125°C ±1 f = dc 130 Channel separation dB f = 100 kHz 110
INPUT BIAS CURRENT
±0.1 ±0.5 IB Input bias current TA = 0°C to 85°C ±0.75 nA TA = –40°C to +125°C ±1 ±0.1 ±0.4 IOS Input offset current TA = 0°C to 85°C ±0.5 nA TA = –40°C to +125°C ±0.6
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 0.2 μVPP f = 10 Hz 8.4 en Input voltage noise density f = 100 Hz 8.1 nV/√Hz f = 1 kHz 8 in Input current noise f = 1 kHz 110 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) + 1 (V+) – 1.4 V Common-mode rejection (V–) + 1 V < V CMRR CM < (V+) – 1.4 V, 124 140 dB ratio TA = –40°C to +125°C
INPUT OVERVOLTAGE
Input overvoltage T protection A = –40℃ to +125℃ (V–) – 40 (V+) + 40 V V 4.8 10 Input current in overvoltage S = 0 V, (V–) – 40 V < V mA protected mode CM < (V+) + 40 V TA = –40℃ to +125℃ See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 9 || 4.4 MΩ || pF ZICM Common-mode 300 || 4.4 GΩ || pF Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: OPA206 OPA2206 OPA4206 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information: OPA206 5.5 Thermal Information: OPA2206 5.6 Thermal Information: OPA4206 5.7 Electrical Characteristics: VS = ±5 V 5.8 Electrical Characteristics: VS = ±15 V 5.9 Typical Characteristics 6 Parameter Measurement Information 6.1 Typical Specifications and Distributions 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Overvoltage Protection 7.3.2 Input Offset Trimming 7.3.3 Lower Input Bias With Super-Beta Inputs 7.3.4 Overload Power Limiter 7.3.5 EMI Rejection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Voltage Attenuator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 8.2.3 Input Buffer and Protection for ADC Driver 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information
SBOSA11E – MARCH 2020 – REVISED DECEMBER 2023
5.7 Electrical Characteristics: VS = ±5 V
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE
±4 ±25 VOS Input offset voltage μV TA = –40°C to +125°C ±55 dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±0.08 ±0.5 μV/°C Power supply rejection ±0.05 ±0.5 PSRR V μV/V ratio S = ±2.25 V to ±18 V TA = –40°C to +125°C ±1 f = dc 130 Channel separation dB f = 100 kHz 110
INPUT BIAS CURRENT
±0.1 ±0.5 IB Input bias current TA = 0°C to 85°C ±0.75 nA TA = –40°C to +125°C ±1 ±0.1 ±0.4 IOS Input offset current TA = 0°C to 85°C ±0.5 nA TA = –40°C to +125°C ±0.6
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 0.2 μVPP f = 10 Hz 8.4 en Input voltage noise density f = 100 Hz 8.1 nV/√Hz f = 1 kHz 8 in Input current noise f = 1 kHz 110 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) + 1 (V+) – 1.4 V Common-mode rejection (V–) + 1 V < V CMRR CM < (V+) – 1.4 V, 124 140 dB ratio TA = –40°C to +125°C
INPUT OVERVOLTAGE
Input overvoltage T protection A = –40℃ to +125℃ (V–) – 40 (V+) + 40 V V 4.8 10 Input current in overvoltage S = 0 V, (V–) – 40 V < V mA protected mode CM < (V+) + 40 V TA = –40℃ to +125℃ See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 9 || 4.4 MΩ || pF ZICM Common-mode 300 || 4.4 GΩ || pF Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: OPA206 OPA2206 OPA4206 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information: OPA206 5.5 Thermal Information: OPA2206 5.6 Thermal Information: OPA4206 5.7 Electrical Characteristics: VS = ±5 V 5.8 Electrical Characteristics: VS = ±15 V 5.9 Typical Characteristics 6 Parameter Measurement Information 6.1 Typical Specifications and Distributions 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Overvoltage Protection 7.3.2 Input Offset Trimming 7.3.3 Lower Input Bias With Super-Beta Inputs 7.3.4 Overload Power Limiter 7.3.5 EMI Rejection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Voltage Attenuator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 8.2.3 Input Buffer and Protection for ADC Driver 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information