Datasheet TDA51S-41HC (Mornsun) - 8

Application circuit Figure10. Typical application PCB Design Instructions 1. The decoupling capacitors and energy storage capacitor of VCC and GND1, VISO and GND2 should be placed as close the chip pins as possible to the chip pins to reduce loop area and parasitic inductance of PCB traces. General control should be within 2mm. The decoupling capacitor is placed close the chip, and the energy storage capacitor is placed outside. As shown in Figre10-1. Storage Storage capacitor Decoupling capacitor Decoupling 22uF capacitor 22uF capacitor IC IC 20mm Not recommended Recommend Figure10-1 2. The power line width should be designed at least 0.5mm when wiring. 3. When it is necessary to place vias in the power supply line and the ground wire, the position of the vias should be placed on the outside of the capacitor relative to the chip pins ,rather than between the capacitor and the chip, as shown in the figure10-2 below to reduce the number of vias effect of parasitic inductance. IC IC Not recommended Recommend Figure10-2 2023.10.26-A/4
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