Datasheet ACT 1 (Actel) - 10

A C T 1 T i m i n g M o d u l e * Input Delay Internal Delays Predicted Output Delay Routing Delays
I/O Module Logic Module I/O Module tINYL = 3.1 ns tIRD2 = 1.4 ns tDLH = 6.7 ns t t IRD1 = 0.9 ns t RD1 = 0.9 ns PD = 2.9 ns t t IRD4 = 3.1 ns ENHZ = 11.6 ns t t RD2 = 1.4 ns t CO = 2.9 ns t IRD8 = 6.6 ns RD4 = 3.1 ns tRD8 = 6.6 ns ARRAY CLOCK tCKH = 5.6 ns FO = 128 FMAX = 70 MHz * Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions.
P r e d i c t a b l e P e r f o r m a n c e : T i g h t D e l a y T i m i n g C h a r a c t e r i s t i c s D i s t r i b u t i o n s
Timing characteristics for ACT 1 devices fall into three Propagation delay between logic modules depends on the categories: family dependent, device dependent, and design resistive and capacitive loading of the routing tracks, the dependent. The input and output buffer characteristics are interconnect elements, and the module inputs being driven. common to all ACT 1 family members. Internal routing delays Propagation delay increases as the length of routing tracks, are device dependent. Design dependency means actual delays the number of interconnect elements, or the number of are not determined until after placement and routing of the inputs increases. user design is complete. Delay values may then be determined From a design perspective, the propagation delay can be by using the DirectTime Analyzer utility or performing statistically correlated or modeled by the fanout (number of simulation with post-layout delays. loads) driven by a module. Higher fanout usually requires
Critical Nets and Typical Nets
some paths to have longer routing tracks. Propagation delays are expressed only for typical nets, which The ACT 1 family delivers a very tight fanout delay are used for initial design performance evaluation. Critical distribution. This tight distribution is achieved in two ways: by net delays can then be applied to the most time-critical paths. decreasing the delay of the interconnect elements and by Critical nets are determined by net property assignment prior decreasing the number of interconnect elements per path. to placement and routing. Up to 6% of the nets in a design may Actel’s patented PLICE antifuse offers a very low be designated as critical, while 90% of the nets in a design are resistive/capacitive interconnect. The ACT 1 family’s typical. antifuses, fabricated in 1.0 micron lithography, offer nominal
Long Tracks
levels of 200 ohms resistance and 7.5 femtofarad (fF) capacitance per antifuse. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or The ACT 1 fanout distribution is also tight due to the low modules. Long tracks employ three and sometimes four number of antifuses required for each interconnect path. The antifuse connections. This increases capacitance and ACT 1 family’s proprietary architecture limits the number of resistance, resulting in longer net delays for macros antifuses per path to a maximum of four, with 90% of connected to long tracks. Typically, up to 6% of nets in a fully interconnects using two antifuses. utilized device require long tracks. Long tracks contribute approximately 5 ns to 10 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section.
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Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP