Datasheet LTC1392 (Analog Devices) - 6

制造商Analog Devices
描述Micropower Temperature, Power Supply and Differential Voltage Monitor
页数 / 页12 / 6 — TEST CIRCUITS. Load Circuit for tdDO, tr and tf. Voltage Waveforms for …
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TEST CIRCUITS. Load Circuit for tdDO, tr and tf. Voltage Waveforms for DOUT Delay Time, tdDO

TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Delay Time, tdDO

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LTC1392
TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Delay Time, tdDO
1.4V CLK VIL 3k tdDO DOUT TEST POINT VOH 100pF DOUT VOL LTC1392 • TC02 LTC1392 • TC03
Voltage Waveforms for DOUT Rise and Fall Times, tr and tf Voltage Waveforms for tdis
VOH DOUT VOL CS 2.0V tr tf 1392 TC04 DOUT 90% WAVEFORM 1 (SEE NOTE 1)
Load Circuit for tdis and ten
tdis DOUT TEST POINT WAVEFORM 2 10% (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH 5V t THAT THE OUTPUT IS HIGH UNTIL DISABLED BY THE OUTPUT CONTROL. 3k dis WAVEFORM 2, ten NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH DOUT THAT THE OUTPUT IS LOW UNTIL DISABLED BY THE OUTPUT CONTROL. tdis WAVEFORM 1 LTC1392 • TC06 100pF LTC1392 • TC05
U U W U APPLICATIONS INFORMATION
The LTC1392 is a micropower data acquisition system
DIGITAL CONSIDERATIONS
designed to measure temperature, an on-chip power supply voltage and a differential input voltage. The LTC1392
Serial Interface
contains the following functional blocks: The LTC1392 communicates with microprocessors and 1. On-chip temperature sensor other external circuitry via a synchronous, half-duplex, 3-wire serial interface (see Figure 1). The clock (CLK) 2. 10-bit successive approximation capacitive ADC synchronizes the data transfer with each bit being trans- 3. Bandgap reference mitted on the falling CLK edge and captured on the rising 4. Analog multiplexer (MUX) CLK edge in both transmitting and receiving systems. The input data is first received and then the A/D conversion 5. Sample-and-hold (S/H) result is transmitted (half-duplex). Half-duplex operation 6. Synchronous, half-duplex serial interface allows DIN and DOUT to be tied together allowing transmis- 7. Control and timing logic sion over three wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 80µs delay is needed for 6