Datasheet LTC3850-2 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Dual, 2-Phase Synchronous Step-Down Switching Controller |
| 页数 / 页 | 36 / 8 — PIN FUNCTIONS. RUN1, RUN2 (Pin 1, Pin 13):. PGOOD (Pin 15):. PGND (Pin … |
| 文件格式/大小 | PDF / 417 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. RUN1, RUN2 (Pin 1, Pin 13):. PGOOD (Pin 15):. PGND (Pin 19):. SENSE1+, SENSE2+ (Pin 2, Pin 12):. INTV. CC (Pin 21):
该数据表的模型线
文件文字版本
LTC3850-2
PIN FUNCTIONS RUN1, RUN2 (Pin 1, Pin 13):
Run Control Inputs. A voltage
PGOOD (Pin 15):
Power Good Indicator Output. Open-drain above 1.2V on either pin turns on the IC. However, forcing logic out that is pulled to ground when either channel either of these pins below 1.2V causes the IC to shut down output exceeds the ±7.5% regulation window, after the that particular channel. There are 0.5μA pull-up currents internal 17μs power bad mask timer expires. for these pins. Once the RUN pin rises above 1.2V, an
PGND (Pin 19):
Power Ground Pin. Connect this pin closely additional 4.5μA pull-up current is added to the pin. to the sources of the bottom N-channel MOSFETs, the (–)
SENSE1+, SENSE2+ (Pin 2, Pin 12):
Current Sense terminal of CVCC and the (–) terminal of CIN. Comparator Inputs. The (+) inputs to the current
INTV
comparators are normally connected to DCR sensing
CC (Pin 21):
Internal 5V Regulator Output. The con- trol circuits are powered from this voltage. Decouple this networks or current sensing resistors. pin to PGND with a 4.7μF low ESR tantalum or ceramic
SENSE1–, SENSE2– (Pin 3, Pin 11):
Current Sense capacitor. Comparator Inputs. The (–) inputs to the current
V
comparators are connected to the outputs.
IN (Pin 22):
Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). For applications
TK/SS1, TK/SS2 (Pin 5, Pin 9):
Output Voltage Tracking where the main input power is 5V, tie the VIN and INTVCC and Soft-Start Inputs. When one channel is confi gured to pins together. be master of the two channels, a capacitor to ground at
BG1, BG2 (Pins 23, 20):
Bottom Gate Driver Outputs. These this pin sets the ramp rate for the master channel’s output pins drive the gates of the bottom N-Channel MOSFETs voltage. When the channel is confi gured to be the slave and swings between PGND and INTV of two channels, the V CC. FB voltage of the master channel is reproduced by a resistor divider and applied to this pin.
BOOST1, BOOST2 (Pins 24, 18):
Boosted Floating Driver Internal soft-start currents of 1.3μA charge the soft-start Supplies. The (+) terminal of the boost-strap capacitors capacitors. connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC.
ITH1, ITH2 (Pin 6, Pin 8):
Current Control Thresholds and Error Amplifi er Compensation Points. Each associated
TG1, TG2 (Pins 25, 17):
Top Gate Driver Outputs. These are channels’ current comparator tripping threshold increases the outputs of fl oating drivers with a voltage swing equal with its I to INTV TH control voltage. CC superimposed on the switch nodes voltages.
V SW1, SW2 (Pins 26, 16):
Switch Node Connections to
FB1, VFB2 (Pin 4, Pin 10):
Error Amplifi er Feedback Inputs. These pins receive the remotely sensed feedback Inductors. Voltage swing at these pins are from a body voltages for each channel from external resistive dividers diode voltage drop below ground to VIN. across the outputs.
MODE/PLLIN (Pin 27):
Force Continuous Mode, Burst
SGND (Pin 7):
Signal Ground. All small-signal components Mode, or Pulse-Skipping Mode Selection Pin and and compensation components should connect to this External Synchronization Input to Phase Detector Pin. ground, which in turn connects to PGND at one point. Connect this pin to SGND to force both channels into the continuous mode of operation. Connect to INTVCC
EXTVCC (Pin 14):
External Power Input to an Internal Switch to enable pulse-skipping mode of operation. Leaving the Connected to INTVCC. This switch closes and supplies the pin fl oating will enable Burst Mode operation. A clock on IC power, bypassing the internal low dropout regulator, the pin will force the controller into continuous mode of whenever EXTVCC is higher than 4.7V. Do not exceed 6V operation and synchronize the internal oscillator. on this pin and ensure VIN > VEXTVCC at all times.
FREQ/PLLFLTR (Pin 28):
The Phase-Locked Loop’s Low-Pass Filter is Tied to This Pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. 38502f 8
PIN FUNCTIONS RUN1, RUN2 (Pin 1, Pin 13):
Run Control Inputs. A voltage
PGOOD (Pin 15):
Power Good Indicator Output. Open-drain above 1.2V on either pin turns on the IC. However, forcing logic out that is pulled to ground when either channel either of these pins below 1.2V causes the IC to shut down output exceeds the ±7.5% regulation window, after the that particular channel. There are 0.5μA pull-up currents internal 17μs power bad mask timer expires. for these pins. Once the RUN pin rises above 1.2V, an
PGND (Pin 19):
Power Ground Pin. Connect this pin closely additional 4.5μA pull-up current is added to the pin. to the sources of the bottom N-channel MOSFETs, the (–)
SENSE1+, SENSE2+ (Pin 2, Pin 12):
Current Sense terminal of CVCC and the (–) terminal of CIN. Comparator Inputs. The (+) inputs to the current
INTV
comparators are normally connected to DCR sensing
CC (Pin 21):
Internal 5V Regulator Output. The con- trol circuits are powered from this voltage. Decouple this networks or current sensing resistors. pin to PGND with a 4.7μF low ESR tantalum or ceramic
SENSE1–, SENSE2– (Pin 3, Pin 11):
Current Sense capacitor. Comparator Inputs. The (–) inputs to the current
V
comparators are connected to the outputs.
IN (Pin 22):
Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). For applications
TK/SS1, TK/SS2 (Pin 5, Pin 9):
Output Voltage Tracking where the main input power is 5V, tie the VIN and INTVCC and Soft-Start Inputs. When one channel is confi gured to pins together. be master of the two channels, a capacitor to ground at
BG1, BG2 (Pins 23, 20):
Bottom Gate Driver Outputs. These this pin sets the ramp rate for the master channel’s output pins drive the gates of the bottom N-Channel MOSFETs voltage. When the channel is confi gured to be the slave and swings between PGND and INTV of two channels, the V CC. FB voltage of the master channel is reproduced by a resistor divider and applied to this pin.
BOOST1, BOOST2 (Pins 24, 18):
Boosted Floating Driver Internal soft-start currents of 1.3μA charge the soft-start Supplies. The (+) terminal of the boost-strap capacitors capacitors. connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC.
ITH1, ITH2 (Pin 6, Pin 8):
Current Control Thresholds and Error Amplifi er Compensation Points. Each associated
TG1, TG2 (Pins 25, 17):
Top Gate Driver Outputs. These are channels’ current comparator tripping threshold increases the outputs of fl oating drivers with a voltage swing equal with its I to INTV TH control voltage. CC superimposed on the switch nodes voltages.
V SW1, SW2 (Pins 26, 16):
Switch Node Connections to
FB1, VFB2 (Pin 4, Pin 10):
Error Amplifi er Feedback Inputs. These pins receive the remotely sensed feedback Inductors. Voltage swing at these pins are from a body voltages for each channel from external resistive dividers diode voltage drop below ground to VIN. across the outputs.
MODE/PLLIN (Pin 27):
Force Continuous Mode, Burst
SGND (Pin 7):
Signal Ground. All small-signal components Mode, or Pulse-Skipping Mode Selection Pin and and compensation components should connect to this External Synchronization Input to Phase Detector Pin. ground, which in turn connects to PGND at one point. Connect this pin to SGND to force both channels into the continuous mode of operation. Connect to INTVCC
EXTVCC (Pin 14):
External Power Input to an Internal Switch to enable pulse-skipping mode of operation. Leaving the Connected to INTVCC. This switch closes and supplies the pin fl oating will enable Burst Mode operation. A clock on IC power, bypassing the internal low dropout regulator, the pin will force the controller into continuous mode of whenever EXTVCC is higher than 4.7V. Do not exceed 6V operation and synchronize the internal oscillator. on this pin and ensure VIN > VEXTVCC at all times.
FREQ/PLLFLTR (Pin 28):
The Phase-Locked Loop’s Low-Pass Filter is Tied to This Pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. 38502f 8