Datasheet ADA4961 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Low Distortion, 3.2 GHz, RF DGA |
| 页数 / 页 | 24 / 7 — Data Sheet. ADA4961. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. P U. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 904 Kb |
| 文件语言 | 英语 |
Data Sheet. ADA4961. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. P U. CC4. CC3. CC2. CC1. GND 1. 18 DNC. VIN+ 2. 17 VOUT+. VIN– 3. 16 VOUT–. GND 4
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Data Sheet ADA4961 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P U CC4 CC3 CC2 CC1 V V V V PM PW 24 23 22 21 20 19 GND 1 18 DNC VIN+ 2 17 VOUT+ VIN– 3 ADA4961 16 VOUT– GND 4 TOP VIEW 15 DNC (Not to Scale) GND 5 14 DNC MODE 6 13 LATCH 7 8 9 10 11 12 O K AF A1 A0 DI CL CS S A2/ A4/ A3/ NOTES
003
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT THE EXPOSED PAD TO GROUND.
12454- Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 5 GND Power Supply Ground. Connect to system ground plane. 2, 3 VIN+, VIN− Differential Inputs. 6 MODE Mode Select Pin for Gain Control. Low indicates serial peripheral interface (SPI), and high (up to 3.3 V) indicates parallel interface. 7 SDIO Serial Data Input/Output Pin for SPI Gain Control. 8 A4/CLK Bit A4 for Parallel Gain Control/Serial Clock Pin for SPI Gain Control. 9 A3/CS Bit A3 for Parallel Gain Control/Chip Select Pin for SPI Gain Control. 10 A2/FA Bit A2 for Parallel Gain Control/Fast Attack Pin for SPI Gain Control. 11 A1 Bit A1 for Parallel Gain Control. 12 A0 Bit A0 for Parallel Gain Control. 13 LATCH Latch Input Asserts Parallel Gain Control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. 14, 15, 18 DNC Do Not Connect. Do not connect to this pin. 16, 17 VOUT−, VOUT+ Differential Outputs. 19 PWUP Power-Up Control Input Pin. A logic high (3.3 V) asserts power-up. A logic low asserts power-down. 20 PM Power/Performance Control Input Pin. A logic low indicates high power and high performance, and a logic high indicates low power and nominal performance. Low power mode must be asserted with VMIN = 2.8 V. 21 VCC1 Positive Power Supply. Connect to 5 V or 3.3 V. 22 VCC2 Positive Power Supply. Connect to 5 V or 3.3 V. 23 VCC3 Positive Power Supply. Connect to 5 V or 3.3 V. 24 VCC4 Positive Power Supply. Connect to 5 V or 3.3 V. EPAD Exposed Pad. Connect the exposed pad to ground. Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
003
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT THE EXPOSED PAD TO GROUND.
12454- Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 5 GND Power Supply Ground. Connect to system ground plane. 2, 3 VIN+, VIN− Differential Inputs. 6 MODE Mode Select Pin for Gain Control. Low indicates serial peripheral interface (SPI), and high (up to 3.3 V) indicates parallel interface. 7 SDIO Serial Data Input/Output Pin for SPI Gain Control. 8 A4/CLK Bit A4 for Parallel Gain Control/Serial Clock Pin for SPI Gain Control. 9 A3/CS Bit A3 for Parallel Gain Control/Chip Select Pin for SPI Gain Control. 10 A2/FA Bit A2 for Parallel Gain Control/Fast Attack Pin for SPI Gain Control. 11 A1 Bit A1 for Parallel Gain Control. 12 A0 Bit A0 for Parallel Gain Control. 13 LATCH Latch Input Asserts Parallel Gain Control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. 14, 15, 18 DNC Do Not Connect. Do not connect to this pin. 16, 17 VOUT−, VOUT+ Differential Outputs. 19 PWUP Power-Up Control Input Pin. A logic high (3.3 V) asserts power-up. A logic low asserts power-down. 20 PM Power/Performance Control Input Pin. A logic low indicates high power and high performance, and a logic high indicates low power and nominal performance. Low power mode must be asserted with VMIN = 2.8 V. 21 VCC1 Positive Power Supply. Connect to 5 V or 3.3 V. 22 VCC2 Positive Power Supply. Connect to 5 V or 3.3 V. 23 VCC3 Positive Power Supply. Connect to 5 V or 3.3 V. 24 VCC4 Positive Power Supply. Connect to 5 V or 3.3 V. EPAD Exposed Pad. Connect the exposed pad to ground. Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE