Datasheet AD9680 (Analog Devices) - 3

Data Sheet AD9680 REVISION HISTORY 3/15—Rev. A to Rev. B
Changes to Figure 30 .. 18 Added AD9680-820 ... Universal Deleted Figure 35, Figure 36, and Figure 38 .. 19 Changes to Features Section .. 1 Added AD9680-500 Section and Figure 31 to Figure 36 ... 19 Changes to Table 1 .. 5 Added Figure 37 Through 42 .. 20 Changes to Table 2 .. 6 Added Figure 43 Through 48 .. 21 Changes to Table 3 .. 8 Added Figure 49 Through 54 .. 22 Changes to Table 4 .. 9 Changes to Analog Input Considerations Section and Added Figure 14; Renumbered Sequentially ... 15 Differential Input Configurations Section ... 25 Added AD9680-820 Section and Figure 31 Through Figure 3 ... 19 Added Input Buffer Control Registers (0x018, 0x019, 0x01A, Added Figure 37 Through Figure 42 .. 20 0x935, 0x934, 0x11A) Section, Figure 66, Figure 68, and Table 9; Added Figure 43 Through Figure 48 .. 21 Renumbered Sequentially .. 26 Added Figure 49 Through Figure 54 .. 22 Changes to Analog Input Buffer Controls and SFDR Added Figure 55 .. 23 Optimization Section and Figure 67 .. 26 Changes to Figure 69 and Figure 70 ... 26 Added Figure 69 to Figure 72 .. 27 Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A, Added Figure 73 to Figure 75 .. 28 0x935, 0x934, 0x11A) Section, Table 9, and Figure 93 .. 31 Changes to Table 10 .. 28 Added Figure 99 Through Figure 100 .. 33 Added Input Clock Divider ½ Period Delay Adjust Section and Changes to Table 10 .. 34 Clock Fine Delay Adjust Section ... 30 Changes to Clock Jitter Considerations Section ... 37 Changes to Figure 83 and Temperature Diode Section ... 31 Added Figure 112 .. 37 Added Signal Monitor Section and Figure 86 to Figure 89 ... 33 Changes to Digital Downconverter (DDC) Section ... 42 Changes to Table 11 .. 39 Changes to Table 17 .. 51 Changes to Table 12 to Table 14 .. 40 Changes to Table 36 .. 77 Changes to Table 16 .. 41 Changes to Ordering Guide ... 91 Deleted Figure 65 and Figure 66 ... 45 Changes to Table 17 .. 45
12/14—Rev. 0 to Rev. A
Changes to Table 19 to Table 20 .. 46 Added AD9680-500 ... Universal Changes to Table 22 .. 47 Changes to Features Section and Figure 1 ... 1 Changes to Table 23 .. 49 Changes to General Description Section ... 4 Changes to JESD204B Link Establishment Section ... 53 Changes to Specifications Section and Table 1.. 5 Added Figure 105 to Figure 110 .. 56 Changes to AC Specifications Section and Table 2 ... 6 Changes to Example 1: Full Bandwidth Mode Section .. 60 Changes to Digital Specifications Section .. 8 Added Multichip Synchronization Section, Figure 115 to Changes to Switching Specifications Section and Table 4 ... 9 Figure 117, and Table 28 ... 62 Changes to Table 6, Thermal Characteristics Section, and Added Test Modes Section and Table 29 to Table 33 ... 66 Table 7 ... 11 Changes to Reading the Memory Map Register Table Change to Digital Inputs Description, Table 8 .. 13 Section .. 70 Added AD9680-1000 Section, Figure 10, and Figure 11; Changes to Table 36 .. 71 Renumbered Sequentially .. 14 Changes to Power Supply Recommendations Section, Changes to Figure 6 to Figure 9 ... 14 Figure 118, and Exposed Pad Thermal Heat Slug Added Figure 12 to Figure 14 .. 15 Recommendations Section .. 83 Changes to Figure 15 to Figure 17 .. 15 Changes to Ordering Guide ... 84 Changes to Figure 18 to Figure 21 .. 16 Changes to Figure 25 and Figure 29 ... 17
5/14—Revision 0: Initial Version
Rev. B | Page 3 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE