Datasheet LTC3107 (Analog Devices) - 3

LTC3107
e lecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VAUX = 4V, VBAT = 3.6V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Harvester Start-Up Voltage Using 1:100 Transformer Turns Ratio 20 30 mV Harvester No-Load Input Current Using 1:100 Transformer Turns Ratio, VIN = 20mV, 3 5 mA All Outputs Charged and in Regulation Harvester Input Voltage Range Using 1:100 Transformer Turns Ratio l VSTARTUP 500 mV VBAT Voltage Range l 2.0 4.0 V VBAT Current Limit VOUT = 0V, VAUX = 0V (Battery Insertion) l 2 30 60 mA VOUT = (VBAT – 0.4V) l 30 70 100 mA VBAT Quiescent Current VAUX > VBAT (Harvesting) 80 110 nA VAUX < VBAT (Not Harvesting) 6 7.5 µA VBAT Reverse Current VAUX = 4V, VBAT = 2.0V 0 nA VOUT Voltage (Average) VAUX > VBAT (Harvesting), Relative to VBAT l –70 –30 –15 mV COUT ≥ 47µF VAUX < VBAT (Not Harvesting), Relative to VBAT l –270 –220 –140 mV COUT ≥ 47µF LDO Output Voltage 0.5mA Load l 2.134 2.2 2.266 V LDO Load Regulation IVLDO = 0mA to 2mA 0.8 1.5 % LDO Line Regulation For VOUT from 2.5V to 4V 0.1 0.2 % LDO Dropout Voltage IVLDO = 2mA l 100 200 mV LDO Current Limit VLDO = 0V l 10 20 40 mA VAUX/VSTORE Clamp Voltage Current Into VAUX = 1mA l 4.13 4.3 4.48 V VOUT Quiescent Current VAUX > VOUT > VBAT 10 100 nA VSTORE Leakage Current VSTORE = 4V, VAUX > VSTORE 10 100 nA VSTORE to VOUT Discharge Path Resistance VSTORE = 4V 120 200 Ω VOUT < VBAT –60mV BAT_OFF Threshold (Falling) Measured on VOUT Relative to VBAT –280 –230 –180 mV BAT_OFF Threshold (Rising) Measured on VOUT Relative to VBAT –60 –30 –15 mV BAT_OFF VOL Sink Current = 100µA 0.15 0.2 V BAT_OFF VOH Source Current = 0 VOUT V BAT_OFF Pull-Up Resistance 0.6 1 1.4 MΩ N-Channel MOSFET On-Resistance C2 = 5V (Note 3) 0.5 Ω
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings is calculated from the ambient temperature (TA) and power dissipation may cause permanent damage to the device. Exposure to any Absolute (PD) according to the formula: TJ = TA + (PD • θJA°C/W), where θJA is the Maximum Rating condition for extended periods may affect device package thermal impedance. reliability and lifetime.
Note 3:
Specification is guaranteed by design and not 100% tested in
Note 2:
The LTC3107 is tested under pulsed load conditions such that TJ ≈ production. TA. The LTC3107E is guaranteed to meet specifications from 0°C to 85°C
Note 4:
Failure to solder the exposed backside of the package to the PC junction temperature. Specifications over the –40°C to 125°C operating board ground plane will result in a thermal resistance much higher than junction temperature range are assured by design, characterization 43°C/W. and correlation with statistical process controls. The LTC3107I is
Note 5:
The Absolute Maximum Rating is a DC rating. Under certain guaranteed over the full –40°C to 125°C operating junction temperature conditions in the applications shown, the peak AC voltage on the C1 and range. Note that the maximum ambient temperature consistent with C2 pins may exceed their Absolute Maximum Rating. This behavior is these specifications, is determined by specific operating conditions normal and acceptable because the current into the pin is limited by the in conjunction with board layout, the rated thermal package thermal impedance of the coupling capacitor. resistance and other environmental factors. The junction temperature (TJ) 3107f For more information www.linear.com/LTC3107 3 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts