Datasheet LTC3459 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 10V Micropower Synchronous Boost Converter in ThinSOT |
| 页数 / 页 | 12 / 10 — TYPICAL APPLICATIONS. Figure 5. Charging a SuperCap from a 3.3V Source. … |
| 文件格式/大小 | PDF / 226 Kb |
| 文件语言 | 英语 |
TYPICAL APPLICATIONS. Figure 5. Charging a SuperCap from a 3.3V Source. PACKAGE DESCRIPTION. DC Package
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LTC3459
TYPICAL APPLICATIONS
controlled, preventing any damaging effects of inrush L1 current. Proper heat sinking of the package is required in SW this application as the die may dissipate 100mW to 200mW V V OUT IN VOUT 5V during initial charging. When VOUT is greater than ~3.5V, 1μF 1M 1μF LTC3459 + normal boost mode operation and effi ciency begin, with 3.3V COUT OFF ON SHDN FB 2F the P-channel MOSFET acting as a synchronous switch. GND 332k Average input current is a constant 50mA during charg- 3459 F05 ing, where the current delivered to the SuperCap varies somewhat with duty cycle. Once the SuperCap is charged COUT: MAXWELL TECHNOLOGIES ULTRACAP PC5-5, 2F, 5V L1: 33μH, 1.7Ω TAIYO YUDEN LB2016 to 5V, the LTC3459 begins to regulate and the input cur- rent is reduced to the amount required to support the load
Figure 5. Charging a SuperCap from a 3.3V Source
and/or self discharge of the SuperCap.
PACKAGE DESCRIPTION DC Package 6-Lead Plastic DFN (2mm
×
2mm)
(Reference LTC DWG # 05-08-1703) R = 0.115 0.38 p 0.05 TYP 0.56 p 0.05 4 6 0.675 p0.05 (2 SIDES) 2.50 p0.05 0.61 p0.05 2.00 p0.10 1.15 p0.05 (2 SIDES) (4 SIDES) PIN 1 BAR PACKAGE PIN 1 TOP MARK OUTLINE CHAMFER OF (SEE NOTE 6) EXPOSED PAD 3 (DC6) DFN 1103 1 0.25 p 0.05 0.25 p 0.05 0.200 REF 0.75 p0.05 0.50 BSC 0.50 BSC 1.42 p0.05 1.37 p0.05 (2 SIDES) (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3459fc 10
TYPICAL APPLICATIONS
controlled, preventing any damaging effects of inrush L1 current. Proper heat sinking of the package is required in SW this application as the die may dissipate 100mW to 200mW V V OUT IN VOUT 5V during initial charging. When VOUT is greater than ~3.5V, 1μF 1M 1μF LTC3459 + normal boost mode operation and effi ciency begin, with 3.3V COUT OFF ON SHDN FB 2F the P-channel MOSFET acting as a synchronous switch. GND 332k Average input current is a constant 50mA during charg- 3459 F05 ing, where the current delivered to the SuperCap varies somewhat with duty cycle. Once the SuperCap is charged COUT: MAXWELL TECHNOLOGIES ULTRACAP PC5-5, 2F, 5V L1: 33μH, 1.7Ω TAIYO YUDEN LB2016 to 5V, the LTC3459 begins to regulate and the input cur- rent is reduced to the amount required to support the load
Figure 5. Charging a SuperCap from a 3.3V Source
and/or self discharge of the SuperCap.
PACKAGE DESCRIPTION DC Package 6-Lead Plastic DFN (2mm
×
2mm)
(Reference LTC DWG # 05-08-1703) R = 0.115 0.38 p 0.05 TYP 0.56 p 0.05 4 6 0.675 p0.05 (2 SIDES) 2.50 p0.05 0.61 p0.05 2.00 p0.10 1.15 p0.05 (2 SIDES) (4 SIDES) PIN 1 BAR PACKAGE PIN 1 TOP MARK OUTLINE CHAMFER OF (SEE NOTE 6) EXPOSED PAD 3 (DC6) DFN 1103 1 0.25 p 0.05 0.25 p 0.05 0.200 REF 0.75 p0.05 0.50 BSC 0.50 BSC 1.42 p0.05 1.37 p0.05 (2 SIDES) (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3459fc 10