Datasheet AD8428 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Low Noise, Low Gain Drift, G = 2000 Instrumentation Amplifier |
| 页数 / 页 | 20 / 7 — Data Sheet. AD8428. TYPICAL PERFORMANCE CHARACTERISTICS. 1600. POSITIVE … |
| 修订版 | A |
| 文件格式/大小 | PDF / 363 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8428. TYPICAL PERFORMANCE CHARACTERISTICS. 1600. POSITIVE INPUT IBIAS. 1400. N = 5170. MEAN = 2.12. NEGATIVE INPUT IBIAS
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Data Sheet AD8428 TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted.
1600 1600 POSITIVE INPUT IBIAS 1400 N = 5170 MEAN = 2.12 1400 NEGATIVE INPUT IBIAS SD = 7.332 1200 1200 N = 5171 1000 1000 MEAN = –10.8 SD = 6.67496 S S T 800 T 800 HI HI N = 5171 MEAN = –10.2 600 600 SD = 6.52901 400 400 200 200 0 0
3
–60 –40 –20 0 20 40 60
-00
–60 –40 –20 0 20 40 60
-006 31
V
731
OSI (µV) I
09
BIAS (nA)
097 Figure 3. Typical Distribution of Input Offset Voltage, VS = ±5 V Figure 6. Typical Distribution of Input Bias Current
1600 1600 1400 N = 5169 N = 5171 MEAN = –2.57 1400 MEAN = –0.53 SD = 7.31066 SD = 1.41655 1200 1200 1000 1000 S S T 800 T 800 HI HI 600 600 400 400 200 200 0 0
07
–60 –40 –20 0 20 40 60
04 0
–8 –6 –4 –2 0 2 4 6 8
0 1- 1-
V
73 73
OSI (µV) I
09
OS (nA)
09 Figure 4. Typical Distribution of Input Offset Voltage, VS = ±15 V Figure 7. Typical Distribution of Input Offset Current
1600 1600 N = 5166 1400 N = 3487 MEAN = 0.398 1400 MEAN = –53.9 SD = 0.42707 SD = 86.7774 1200 1200 1000 1000 S T S 800 T 800 HI HI 600 600 400 400 200 200 0 0 –3 –2 –1 0 1 2 3
05 0 08 0 1-
–600 –400 –200 0 200 400 600
31-
V
73
OSI DRIFT (µV/°C)
09
GAIN ERROR (µV/V)
097 Figure 5. Typical Distribution of Input Offset Voltage Drift Figure 8. Typical Distribution of Gain Error, Gain = 2000, VS = ±15 V, RL = 10 kΩ Rev. A | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE FILTER TERMINALS REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION IMAX Input Voltages Beyond the Rails Large Differential Input Voltage at High Gain RADIO FREQUENCY INTERFERENCE (RFI) CALCULATING THE NOISE OF THE INPUT STAGE Source Resistance Noise Voltage Noise of the Instrumentation Amplifier Current Noise of the Instrumentation Amplifier Total Noise Density Calculation APPLICATIONS INFORMATION EFFECT OF PASSIVE NETWORK ACROSS THE FILTER TERMINALS CIRCUITS USING THE FILTER TERMINALS Setting the Amplifier to Different Gains Low-Pass Filter Notch Filter Extracting the Common-Mode Voltage of the Input OUTLINE DIMENSIONS ORDERING GUIDE
VS = ±15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted.
1600 1600 POSITIVE INPUT IBIAS 1400 N = 5170 MEAN = 2.12 1400 NEGATIVE INPUT IBIAS SD = 7.332 1200 1200 N = 5171 1000 1000 MEAN = –10.8 SD = 6.67496 S S T 800 T 800 HI HI N = 5171 MEAN = –10.2 600 600 SD = 6.52901 400 400 200 200 0 0
3
–60 –40 –20 0 20 40 60
-00
–60 –40 –20 0 20 40 60
-006 31
V
731
OSI (µV) I
09
BIAS (nA)
097 Figure 3. Typical Distribution of Input Offset Voltage, VS = ±5 V Figure 6. Typical Distribution of Input Bias Current
1600 1600 1400 N = 5169 N = 5171 MEAN = –2.57 1400 MEAN = –0.53 SD = 7.31066 SD = 1.41655 1200 1200 1000 1000 S S T 800 T 800 HI HI 600 600 400 400 200 200 0 0
07
–60 –40 –20 0 20 40 60
04 0
–8 –6 –4 –2 0 2 4 6 8
0 1- 1-
V
73 73
OSI (µV) I
09
OS (nA)
09 Figure 4. Typical Distribution of Input Offset Voltage, VS = ±15 V Figure 7. Typical Distribution of Input Offset Current
1600 1600 N = 5166 1400 N = 3487 MEAN = 0.398 1400 MEAN = –53.9 SD = 0.42707 SD = 86.7774 1200 1200 1000 1000 S T S 800 T 800 HI HI 600 600 400 400 200 200 0 0 –3 –2 –1 0 1 2 3
05 0 08 0 1-
–600 –400 –200 0 200 400 600
31-
V
73
OSI DRIFT (µV/°C)
09
GAIN ERROR (µV/V)
097 Figure 5. Typical Distribution of Input Offset Voltage Drift Figure 8. Typical Distribution of Gain Error, Gain = 2000, VS = ±15 V, RL = 10 kΩ Rev. A | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE FILTER TERMINALS REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION IMAX Input Voltages Beyond the Rails Large Differential Input Voltage at High Gain RADIO FREQUENCY INTERFERENCE (RFI) CALCULATING THE NOISE OF THE INPUT STAGE Source Resistance Noise Voltage Noise of the Instrumentation Amplifier Current Noise of the Instrumentation Amplifier Total Noise Density Calculation APPLICATIONS INFORMATION EFFECT OF PASSIVE NETWORK ACROSS THE FILTER TERMINALS CIRCUITS USING THE FILTER TERMINALS Setting the Amplifier to Different Gains Low-Pass Filter Notch Filter Extracting the Common-Mode Voltage of the Input OUTLINE DIMENSIONS ORDERING GUIDE