Datasheet PIC10F320, PIC10F322, PIC10LF320, PIC10LF322 (Microchip) - 4

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PIC10(L)F320/322 Table of Contents
1.0 Device Overview .. 6 2.0 Memory Organization ... 9 3.0 Device Configuration .. 19 4.0 Oscillator Module.. 24 5.0 Resets .. 28 6.0 Interrupts .. 35 7.0 Power-Down Mode (Sleep) .. 44 8.0 Watchdog Timer ... 46 9.0 Flash Program Memory Control ... 50 10.0 I/O Port ... 67 11.0 Interrupt-On-Change .. 73 12.0 Fixed Voltage Reference (FVR) ... 77 13.0 Internal Voltage Regulator (IVR) .. 79 14.0 Temperature Indicator Module ... 81 15.0 Analog-to-Digital Converter (ADC) Module .. 83 16.0 Timer0 Module ... 93 17.0 Timer2 Module ... 96 18.0 Pulse-Width Modulation (PWM) Module .. 98 19.0 Configurable Logic Cell (CLC).. 104 20.0 Numerically Controlled Oscillator (NCO) Module ... 119 21.0 Complementary Waveform Generator (CWG) Module .. 129 22.0 In-Circuit Serial Programming™ (ICSP™) ... 144 23.0 Instruction Set Summary .. 147 24.0 Electrical Specifications.. 156 25.0 DC and AC Characteristics Graphs and Charts ... 176 26.0 Development Support... 177 27.0 Packaging Information.. 181 Appendix A: Data Sheet Revision History.. 189 DS40001585D-page 4  2011-2015 Microchip Technology Inc. Document Outline High-Performance RISC CPU Memory Special Microcontroller Features eXtreme Low-Power (XLP) Features (PIC10LF320/322) Peripheral Features PIC10(L)F320/322 Family Types FIGURE 1: 6-Pin Diagram, PIC10(L)F320/322 FIGURE 2: 8-Pin Diagram, PIC10(L)F320/322 TABLE 1: 6 and 8-Pin Allocation Table, PIC10(L)F320/322 Table of Contents Most Current Data Sheet Errata Customer Notification System 6/8-Pin Flash-Based, 8-Bit Microcontrollers 1.0 Device Overview TABLE 1-1: Device Peripheral Summary FIGURE 1-1: PIC10(L)F320/322 Block Diagram TABLE 1-2: PIC10(L)F320/322 Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization TABLE 2-1: Device Sizes and Addresses FIGURE 2-1: Program Memory Map And Stack For PIC10(L)F320 FIGURE 2-2: Program Memory Map And Stack For PIC10(L)F322 2.2 Data Memory Organization Register 2-1: STATUS: STATUS Register TABLE 2-2: PIC10(L)F320/322 Memory Map (Bank 0) TABLE 2-3: Special Function Register Summary (Bank 0) 2.3 PCL and PCLATH FIGURE 2-3: Loading of PC in Different Situations 2.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing FIGURE 2-4: Direct/Indirect Addressing PIC10(L)F320/322 3.0 Device Configuration 3.1 Configuration Word 3.2 Register Definitions: Configuration Word Register 3-1: CONFIG: Configuration Word 3.3 Code Protection 3.4 Write Protection 3.5 User ID 3.6 Device ID and Revision ID 3.7 Register Definitions: Device and Revision Register 3-2: DEVID: Device ID Register(1) 4.0 Oscillator Module 4.1 Overview FIGURE 4-1: PIC10(L)F320/322 Clock Source Block Diagram 4.2 Clock Source Modes 4.3 Internal Clock Modes 4.4 Register Definitions: Reference Clock Control Register 4-1: CLKRCON – Reference Clock Control Register 4.5 Register Definitions: Oscillator Control Register 4-2: OSCCON: Oscillator Control Register 4.6 External Clock Mode TABLE 4-1: Summary of Registers Associated with Clock Sources TABLE 4-2: Summary of Configuration Word with Clock Sources 5.0 Resets FIGURE 5-1: Simplified Block Diagram Of On-Chip Reset Circuit 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) TABLE 5-1: BOR Operating Modes FIGURE 5-2: Brown-Out Situations 5.3 Register Definition: BOR Control Register 5-1: BORCON: Brown-out Reset Control Register 5.4 Low-Power Brown-out Reset (LPBOR) 5.5 MCLR TABLE 5-2: MCLR Configuration 5.6 Watchdog Timer (WDT) Reset 5.7 Programming Mode ICSP Exit 5.8 Power-Up Timer 5.9 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.10 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.11 Power Control (PCON) Register 5.12 Register Definition: Power Control Register 5-2: PCON: Power Control Register TABLE 5-5: Summary Of Registers Associated With Resets TABLE 5-6: Summary of Configuration Word with Resets 6.0 Interrupts FIGURE 6-1: Interrupt Logic 6.1 Operation 6.2 Interrupt Latency FIGURE 6-2: Interrupt Latency FIGURE 6-3: INT Pin Interrupt Timing 6.3 Interrupts During Sleep 6.4 INT Pin 6.5 Context Saving During Interrupts EXAMPLE 6-1: Saving Status and W Registers in RAM 6.6 Interrupt Control Registers Register 6-1: INTCON: Interrupt Control Register Register 6-2: PIE1: Peripheral Interrupt Enable Register 1 Register 6-3: PIR1: Peripheral Interrupt Request Register 1 TABLE 6-1: Summary of Registers Associated with Interrupts 7.0 Power-Down Mode (Sleep) 7.1 Wake-up from Sleep FIGURE 7-1: Wake-up From Sleep through Interrupt TABLE 7-1: Summary of Registers Associated with power-down Mode 8.0 Watchdog Timer FIGURE 8-1: Watchdog Timer Block Diagram 8.1 Independent Clock Source 8.2 WDT Operating Modes TABLE 8-1: WDT Operating Modes 8.3 Time-Out Period 8.4 Clearing the WDT 8.5 Operation During Sleep TABLE 8-2: WDT Clearing Conditions 8.6 Watchdog Control Register Register 8-1: WDTCON: Watchdog Timer Control Register TABLE 8-3: Summary of Registers Associated with Watchdog Timer TABLE 8-4: Summary of cONFIGURATION wORD with Watchdog Timer 9.0 Flash Program Memory Control 9.1 PMADRL and PMADRH Registers 9.2 Flash Program Memory Overview TABLE 9-1: Flash Memory Organization By Device FIGURE 9-1: Flash Program Memory Read Flowchart FIGURE 9-2: Flash Program Memory Read Cycle Execution EXAMPLE 9-1: Flash PROGRAM MEMORY Read FIGURE 9-3: Flash Program Memory Unlock Sequence Flowchart FIGURE 9-4: Flash Program Memory Erase Flowchart EXAMPLE 9-2: Erasing One Row of Program Memory FIGURE 9-5: Block WRITES to Flash Program Memory With 16 write latches FIGURE 9-6: Flash Program Memory Write Flowchart EXAMPLE 9-3: Writing to Flash Program Memory 9.3 Modifying Flash Program Memory FIGURE 9-7: Flash Program Memory Modify Flowchart 9.4 User ID, Device ID and Configuration Word Access TABLE 9-2: User ID, Device ID and Configuration Word Access (cfgs = 1) EXAMPLE 9-4: Configuration Word and Device ID Access 9.5 Write Verify FIGURE 9-8: Flash Program Memory Verify Flowchart 9.6 Flash Program Memory Control Registers Register 9-1: PMDATL: Program Memory Data Low Register 9-2: PMDATH: Program Memory Data hIGH Register 9-3: PMADRL: Program Memory Address Low Register 9-4: PMADRH: Program Memory Address hIGH Register 9-5: PMCON1: Program Memory Control 1 Register Register 9-6: PMCON2: Program Memory Control 2 Register TABLE 9-3: Summary of Registers Associated with Flash Program Memory TABLE 9-4: Summary of cONFIGURATION wORD with Flash Program Memory 10.0 I/O Port FIGURE 10-1: I/O Port Operation EXAMPLE 10-1: Initializing PORTA 10.1 PORTA Registers TABLE 10-1: PORTA Output Priority 10.2 Register Definitions: PORTA Register 10-1: PORTA: PORTA Register Register 10-2: TRISA: PORTA Tri-State Register Register 10-3: LATA: PORTA Data Latch Register Register 10-4: ANSELA: PORTA Analog Select Register Register 10-5: WPUA: Weak Pull-UP PORTA Register TABLE 10-2: Summary of Registers Associated with PORTA 11.0 Interrupt-On-Change 11.1 Enabling the Module 11.2 Individual Pin Configuration 11.3 Interrupt Flags 11.4 Clearing Interrupt Flags EXAMPLE 11-1: Clearing Interrupt Flags 11.5 Operation in Sleep FIGURE 11-1: Interrupt-On-Change Block Diagram 11.6 Interrupt-On-Change Registers Register 11-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 11-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 11-3: IOCAF: Interrupt-on-Change PORTA Flag Register TABLE 11-1: Summary of Registers Associated with Interrupt-on-Change 12.0 Fixed Voltage Reference (FVR) 12.1 Independent Gain Amplifiers 12.2 FVR Stabilization Period FIGURE 12-1: Voltage Reference Block Diagram TABLE 12-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 12.3 FVR Control Registers Register 12-1: FVRCON: Fixed Voltage Reference Control Register TABLE 12-2: Summary of Registers Associated with Fixed Voltage Reference 13.0 Internal Voltage Regulator (IVR) TABLE 13-1: IVR Power modes - REGULATED Register 13-1: VREGCON: Voltage Regulator Control Register 14.0 Temperature Indicator Module 14.1 Circuit Operation FIGURE 14-1: Temperature Circuit Diagram 14.2 Minimum Operating Vdd vs. Minimum Sensing Temperature TABLE 14-1: Recommended Vdd vs. Range 14.3 Temperature Output 14.4 ADC Acquisition Time TABLE 14-2: Summary of Registers Associated with the Temperature Indicator 15.0 Analog-to-Digital Converter (ADC) Module FIGURE 15-1: ADC Simplified Block Diagram 15.1 ADC Configuration TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles 15.2 ADC Operation 15.3 ADC Register Definitions Register 15-1: ADCON: A/D Control Register 0 Register 15-2: ADRES: ADC Result Register 15.4 A/D Acquisition Requirements FIGURE 15-3: Analog Input Model FIGURE 15-4: ADC Transfer Function TABLE 15-2: Summary of Registers Associated with ADC 16.0 Timer0 Module 16.1 Timer0 Operation FIGURE 16-1: Block Diagram of the Timer0 Prescaler Register 16-1: OPTION_REG: OPTION Register TABLE 16-1: Summary of Registers Associated with Timer0 17.0 Timer2 Module 17.1 Timer2 Operation FIGURE 17-1: Timer2 Block Diagram Register 17-1: T2CON: Timer2 Control Register TABLE 17-1: Summary of Registers Associated With Timer2 18.0 Pulse-Width Modulation (PWM) Module FIGURE 18-1: Simplified PWM Block Diagram FIGURE 18-2: PWM Output 18.1 PWMx Pin Configuration TABLE 18-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 18-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 18.2 PWM Register Definitions Register 18-1: PWMxCON: PWM Control Register Register 18-2: PWMXDCH: PWM Duty Cycle High Bits Register 18-3: PWMxDCL: PWM Duty Cycle LOW Bits TABLE 18-3: Summary of Registers Associated with PWM 19.0 Configurable Logic Cell (CLC) FIGURE 19-1: CLCx Simplified Block Diagram 19.1 CLCx Setup TABLE 19-1: CLCx Data Input Selection TABLE 19-2: Data gating Logic 19.2 CLCx Interrupts 19.3 Effects of a Reset 19.4 Operation During Sleep FIGURE 19-2: Input Data Selection and Gating FIGURE 19-3: Programmable Logic Functions 19.5 CLC Control Registers Register 19-1: CLCxCON: Configurable Logic CELL Control Register Register 19-2: CLCxPOL: Signal Polarity Control Register Register 19-3: CLCxSEL0: MULTIPLEXER DATA 1 and 2 SELECT Register Register 19-4: CLCxSEL1: MULTIPLEXER DATA 3 and 4 SELECT Register Register 19-5: CLCxGLS0: Gate 1 Logic Select Register Register 19-6: CLCxGLS1: Gate 2 Logic Select Register Register 19-7: CLCxGLS2: Gate 3 Logic Select Register Register 19-8: CLCxGLS3: Gate 4 Logic Select Register TABLE 19-3: Summary Of Registers Associated With CLCx 20.0 Numerically Controlled Oscillator (NCO) Module FIGURE 20-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram 20.1 NCOx OPERATION 20.2 FIXED DUTY CYCLE (FDC) MODE 20.3 PULSE FREQUENCY (PF) MODE 20.4 OUTPUT POLARITY CONTROL FIGURE 20-2: NCO – Fixed Duty Cycle (FDC) and Pulse Frequency Mode (PFM) Output Operation Diagram 20.5 Interrupts 20.6 Effects of a Reset 20.7 Operation In Sleep 20.8 NCOx Control Registers Register 20-1: NCOxCON: NCOx Control Register Register 20-2: NCOxCLK: NCOx Input Clock Control Register Register 20-3: NCOxACCL: NCOx Accumulator Register – Low Byte Register 20-4: NCOxACCH: NCOx Accumulator Register – High Byte Register 20-5: NCOxACCU: NCOx Accumulator Register – Upper Byte Register 20-6: NCOxINCL: NCOx Increment Register – Low Byte Register 20-7: NCOxINCH: NCOx Increment Register – High Byte TABLE 20-1: Summary of Registers Associated with NCOx 21.0 Complementary Waveform Generator (CWG) Module FIGURE 21-1: CWG Block Diagram FIGURE 21-2: Typical CWG Operation with PWM1 (no Auto-shutdown) 21.1 Fundamental Operation 21.2 Clock Source 21.3 Selectable Input Sources 21.4 Output Control 21.5 Dead-Band Control 21.6 Rising Edge Dead Band 21.7 Falling Edge Dead Band 21.8 Dead-Band Uncertainty FIGURE 21-3: Dead-band Operation, CWGxDBR = 01H, CWGxDBF = 02H FIGURE 21-4: Dead-band Operation, CWGxDBR = 03H, CWGxDBF = 04H, Source shorter than dead band EXAMPLE 21-1: Dead-band Delay time Uncertainty 21.9 Auto-shutdown Control 21.10 Operation During Sleep 21.11 Configuring the CWG FIGURE 21-5: SHUTDOWN Functionality, Auto-restart Disabled (GxARSEN = 0) FIGURE 21-6: SHUTDOWN Functionality, Auto-restart Enabled (GxARSEN = 1) 21.12 CWG Control Registers Register 21-1: CWGxCON0: CWG Control Register 0 Register 21-2: CWGxCON1: CWG Control Register 1 Register 21-3: CWGXCON2: CWG Control Register 2 Register 21-4: CWGxDBR: Complementary Waveform Generator (CWGx) Rising Dead-band Count Register Register 21-5: CWGxdbf: Complementary Waveform Generator (CWGx) Falling Dead-band Count Register TABLE 21-1: Summary of Registers Associated with CWG 22.0 In-Circuit Serial Programming™ (ICSP™) 22.1 High-Voltage Programming Entry Mode 22.2 Low-Voltage Programming Entry Mode 22.3 Common Programming Interfaces FIGURE 22-1: ICD RJ-11 Style Connector Interface FIGURE 22-2: PICkit™ Style Connector Interface FIGURE 22-3: Typical connection for ICSP™ programming 23.0 Instruction Set Summary 23.1 Read-Modify-Write Operations TABLE 23-1: Opcode Field Descriptions FIGURE 23-1: General Format for Instructions TABLE 23-2: Instruction Set 23.2 Instruction Descriptions 24.0 Electrical Specifications 24.1 Absolute Maximum Ratings(†) 24.2 Standard Operating Conditions FIGURE 24-1: PIC10F320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C FIGURE 24-2: PIC10LF320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C 24.3 DC Characteristics TABLE 24-1: Supply Voltage FIGURE 24-3: POR and POR Rearm with Slow Rising Vdd TABLE 24-2: Supply Voltage (Idd)(1,2) TABLE 24-3: Power-Down Currents (Ipd)(1,2) TABLE 24-4: I/O Ports TABLE 24-5: Memory Programming Requirements 24.4 Thermal Considerations 24.5 AC Characteristics FIGURE 24-4: Load Conditions FIGURE 24-5: Clock Timing TABLE 24-6: Clock Oscillator Timing Requirements TABLE 24-7: Oscillator Parameters FIGURE 24-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature FIGURE 24-7: CLKR and I/O Timing TABLE 24-8: CLKR and I/O Timing Parameters FIGURE 24-8: Reset, Watchdog Timer, and Power-up Timer Timing FIGURE 24-9: Brown-Out Reset Timing and Characteristics TABLE 24-9: Reset, Watchdog Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 24-10: Timer0 and Timer1 External Clock Timings TABLE 24-10: Timer0 External Clock Requirements FIGURE 24-11: CLC Propagation Timing TABLE 24-11: Configuration Logic Cell (CLC) Characteristics TABLE 24-12: A/D Converter (ADC) Characteristics: TABLE 24-13: A/D Conversion Requirements FIGURE 24-12: A/D Conversion Timing (Normal Mode) FIGURE 24-13: A/D Conversion Timing (Sleep Mode) 25.0 DC and AC Characteristics Graphs and Charts 26.0 Development Support 26.1 MPLAB X Integrated Development Environment Software 26.2 MPLAB XC Compilers 26.3 MPASM Assembler 26.4 MPLINK Object Linker/ MPLIB Object Librarian 26.5 MPLAB Assembler, Linker and Librarian for Various Device Families 26.6 MPLAB X SIM Software Simulator 26.7 MPLAB REAL ICE In-Circuit Emulator System 26.8 MPLAB ICD 3 In-Circuit Debugger System 26.9 PICkit 3 In-Circuit Debugger/ Programmer 26.10 MPLAB PM3 Device Programmer 26.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 26.12 Third-Party Development Tools 27.0 Packaging Information 27.1 Package Marking Information TABLE 27-1: 8-Lead 2X3 dfn (mc) tOP Marking TABLE 27-2: 6-Lead SOT-23 (OT) Package Top Marking 27.2 Package Details Appendix A: Data Sheet Revision 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