Datasheet ADA4940-2 (Analog Devices) - 8

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ADA4940-1/ADA4940-2 Data Sheet ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 9.
quiescent power dissipation and the power dissipated in the
Parameter Rating
package due to the load drive for al outputs. The quiescent Supply Voltage 8 V power dissipation is the voltage between the supply pins (±VS) VOCM ±VS times the quiescent current (IS). The load current consists of the Differential Input Voltage 1.2 V differential and common-mode currents flowing to the load, as Operating Temperature Range −40°C to +125°C well as currents flowing through the external feedback networks Storage Temperature Range −65°C to +150°C and internal common-mode feedback loop. The internal Lead Temperature (Soldering, 10 sec) 300°C resistor tap used in the common-mode feedback loop places a Junction Temperature 150°C negligible differential load on the output. RMS voltages and ESD currents should be considered when dealing with ac signals. Field Induced Charged Device Model (FICDM) 1250 V Airflow reduces θ Human Body Model (HBM) 2000 V JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, Stresses above those listed under Absolute Maximum Ratings and power planes reduces the θJA. may cause permanent damage to the device. This is a stress Figure 3 shows the maximum safe power dissipation in the rating only; functional operation of the device at these or any package vs. the ambient temperature for the 8-lead SOIC (θ other conditions above those indicated in the operational JA = 158°C/W, single) the 16-lead LFCSP (θ section of this specification is not implied. Exposure to absolute JA = 91.3°C/W, single) and 24-lead LFCSP (θ maximum rating conditions for extended periods may affect JA = 65.1°C/W, dual) packages on a JEDEC standard 4-layer board. θ device reliability. JA values are approximations.
3.5 THERMAL RESISTANCE
θ
)
JA is specified for the worst-case conditions, that is, θJA is
3.0
specified for the device soldered on a circuit board in stil air.
(W N ADA4940-2 (LFCSP) IO T 2.5 Table 10. PA ADA4940-1 (LFCSP) Package Type θ 2.0 JA Unit ISSI D
8-Lead SOIC (Single)/4-Layer Board 158 °C/W
ER
16-Lead LFCSP (Single)/4-Layer Board 91.3 °C/W
W 1.5
24-Lead LFCSP (Dual)/4-Layer Board 65.1 °C/W
M PO 1.0 MU XI ADA4940-1 (SOIC) MAXIMUM POWER DISSIPATION MA 0.5
The maximum safe power dissipation in the ADA4940-1/ ADA4940-2 packages is limited by the associated rise in
0 –40 –20 0 20 40 60 80 100 120
004 junction temperature (TJ) on the die. At approximately 150°C,
AMBIENT TEMPERATURE (°C)
08452- which is the glass transition temperature, the plastic changes its Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the
ESD CAUTION
ADA4940-1/ADA4940-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. C | Page 8 of 32 Document Outline Features Applications General Description Functional Block Diagrams Revision History Specifications VS = 5 V +DIN or –DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance VS = 3 V +DIN or –DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Definition of Terms Differential Voltage Common-Mode Voltage (CMV) Common-Mode Offset Voltage Differential VOS, Differential CMRR, and VOCM CMRR Balance Theory of Operation Applications Information Analyzing an Application Circuit Setting the Closed-Loop Gain Estimating the Output Noise Voltage Impact of Mismatches in the Feedback Networks Calculating the Input Impedance of an Application Circuit Terminating a Single-Ended Input Input Common-Mode Voltage Range Input and Output Capacitive AC Coupling Setting the Output Common-Mode Voltage DISABLE Pin Driving a Capacitive Load Driving a High Precision ADC Layout, Grounding, and Bypassing ADA4940-1 LFCSP Example Outline Dimensions Ordering Guide