Datasheet 74HC4053, 74HCT4053 (NXP)
| 制造商 | NXP |
| 描述 | Triple 2-channel analog multiplexer/demultiplexer |
| 页数 / 页 | 31 / 1 — 74HC4053; 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer. … |
| 文件格式/大小 | PDF / 334 Kb |
| 文件语言 | 英语 |
74HC4053; 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer. Rev. 9 — 10 February 2016. Product data sheet
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74HC4053; 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer Rev. 9 — 10 February 2016 Product data sheet 1. General description
The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E) is common to all switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V Complies with JEDEC standard no. 7A Low ON resistance: 80 (typical) at V CC VEE = 4.5 V 70 (typical) at V CC VEE = 6.0 V 60 (typical) at V CC VEE = 9.0 V Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical ‘break before make’ built-in ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1 Additional dynamic characteristics 12. Package outline 13. Abbreviations 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents
The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E) is common to all switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V Complies with JEDEC standard no. 7A Low ON resistance: 80 (typical) at V CC VEE = 4.5 V 70 (typical) at V CC VEE = 6.0 V 60 (typical) at V CC VEE = 9.0 V Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical ‘break before make’ built-in ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1 Additional dynamic characteristics 12. Package outline 13. Abbreviations 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents