Datasheet ATmega64, ATmega64L - Complete (Atmel) - 3

ATmega64(L) Overview
The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
Block Diagram Figure 2.
Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS AVCC DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTF REG. PORTF PORTA REG. PORTA PORTC REG. PORTC 8-BIT DATA BUS XTAL1 AREF CALIB. OSC INTERNAL ADC OSCILLATOR XTAL2 OSCILLATOR PROGRAM STACK WATCHDOG JTAG TAP COUNTER POINTER TIMER OSCILLATOR PROGRAM SRAM MCU CONTROL TIMING AND ON-CHIP DEBUG FLASH REGISTER CONTROL RESET BOUNDARY- INSTRUCTION TIMER/ SCAN GENERAL REGISTER COUNTERS PURPOSE REGISTERS X PROGRAMMING PEN INSTRUCTION Y INTERRUPT LOGIC DECODER Z UNIT CONTROL ALU EEPROM LINES STATUS REGISTER USART0 SPI 2-WIRE SERIAL USART1 INTERFACE R O T DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REG. DATA DIR. ARA + - PORTE REG. PORTE PORTB REG. PORTB PORTD REG. PORTD PORTG REG. PORTG ANALOG COMP PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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2490R–AVR–02/2013 Document Outline Features Pin Configuration Disclaimer Overview Block Diagram ATmega103 and ATmega64 Compatibility ATmega103 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) Port G (PG4..PG0) RESET XTAL1 XTAL2 AVCC AREF PEN Resources Data Retention About Code Examples AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register SREG – AVR Status Register General Purpose Register File X-, Y-, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access EEARH and EEARL – EEPROM Address Register EEDR – EEPROM Data Register EECR – EEPROM Control Register EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory External Memory Interface Overview ATmega103 Compatibility Using the External Memory Interface Address Latch Requirements Pull-up and Bus Keeper Timing XMEM Register Description MCUCR – MCU Control Register XMCRA – External Memory Control Register A XMCRB – External Memory Control Register B Using all Locations of External Memory Smaller than 64 Kbytes Using all 64Kbytes Locations of External Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Asynchronous Timer Clock – clkASY ADC Clock – clkADC Clock Sources XDIV – XTAL Divide Control Register Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator OSCCAL – Oscillator Calibration Register(1) External Clock Timer/Counter Oscillator Power Management and Sleep Modes MCUCR – MCU Control Register Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode Standby Mode Extended Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins JTAG Interface and On-chip Debug System System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCUCSR – MCU Control and Status Register(1) Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer WDTCR – Watchdog Timer Control Register Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 Interrupts Interrupt Vectors in ATmega64 Moving Interrupts Between Application and Boot Space MCUCR – MCU Control Register I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Alternate Port Functions SFIOR – Special Function IO Register Alternate Functions of Port A Alternate Functions of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Alternate Functions of Port F Alternate Functions of Port G Register Description for I/O Ports PORTA – Port A Data Register DDRA – Port A Data Direction Register PINA – Port A Input Pins Address PORTB – Port B Data Register DDRB – Port B Data Direction Register PINB – Port B Input Pins Address PORTC – Port C Data Register DDRC – Port C Data Direction Register PINC – Port C Input Pins Address PORTD – Port D Data Register DDRD – Port D Data Direction Register PIND – Port D Input Pins Address PORTE – Port E Data Register DDRE – Port E Data Direction Register PINE – Port E Input Pins Address PORTF – Port F Data Register DDRF – Port F Data Direction Register PINF – Port F Input Pins Address PORTG – Port G Data Register DDRG – Port G Data Direction Register PING – Port G Input Pins Address External Interrupts EICRA – External Interrupt Control Register A EICRB – External Interrupt Control Register B EIMSK – External Interrupt Mask Register EIFR – External Interrupt Flag Register 8-bit Timer/Counter0 with PWM and Asynchronous Operation Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description TCCR0 – Timer/Counter Control Register TCNT0 – Timer/Counter Register OCR0 – Output Compare Register Asynchronous Operation of the Timer/Counter ASSR – Asynchronous Status Register Asynchronous Operation of Timer/Counter0 TIMSK – Timer/Counter Interrupt Mask Register TIFR – Timer/Counter Interrupt Flag Register Timer/Counter Prescaler SFIOR – Special Function IO Register 16-bit Timer/Counter (Timer/Counter 1 and Timer/Counter3 ) Restrictions in ATmega103 Compatibility Mode Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description TCCR1A – Timer/Counter1 Control Register A TCCR3A – Timer/Counter3 Control Register A TCCR1B – Timer/Counter1 Control Register B TCCR3B – Timer/Counter3 Control Register B TCCR1C – Timer/Counter1 Control Register C TCCR3C – Timer/Counter3 Control Register C TCNT1H and TCNT1L – Timer/Counter1 TCNT3H and TCNT3L – Timer/Counter3 OCR1AH and OCR1AL –Output Compare Register 1 A OCR1BH and OCR1BL – Output Compare Register 1 B OCR1CH and OCR1CL – Output Compare Register 1 C OCR3AH and OCR3AL – Output Compare Register 3 A OCR3BH and OCR3BL – Output Compare Register 3 B OCR3CH and OCR3CL – Output Compare Register 3 C ICR1H and ICR1L – Input Capture Register 1 ICR3H and ICR3L – Input Capture Register 3 TIMSK – Timer/Counter Interrupt Mask Register(1) ETIMSK – Extended Timer/Counter Interrupt Mask Register(1) TIFR – Timer/Counter Interrupt Flag Register(1) ETIFR – Extended Timer/Counter Interrupt Flag Register Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source SFIOR – Special Function IO Register 8-bit Timer/Counter2 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description TCCR2 – Timer/Counter Control Register TCNT2 – Timer/Counter Register OCR2 – Output Compare Register TIMSK – Timer/Counter Interrupt Mask Register TIFR – Timer/Counter Interrupt Flag Register Output Compare Modulator (OCM1C2) Overview Description Timing Example SPI – Serial Peripheral Interface SS Pin Functionality Slave Mode Master Mode SPCR – SPI Control Register SPSR – SPI Status Register SPDR – SPI Data Register Data Modes USART Dual USART Overview AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2Xn) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bits Sending Frames with 9 Data Bits Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM USART Register Description UDRn – USART I/O Data Register UCSRnA – USART Control and Status Register A UCSRnB – USART Control and Status Register B UCSRnC – USART Control and Status Register C(1) UBRRnL and UBRRnH – USART Baud Rate Registers(1) Examples of Baud Rate Setting TWI – Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions Address Packet Format Data Packet Format Combining Address and Data Packets Into a Transmission Multi-master Bus Systems, Arbitration and Synchronization Overview of the TWI Module SCL and SDA Pins Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit TWI Register Description TWBR –TWI Bit Rate Register TWCR – TWI Control Register TWSR – TWI Status Register TWDR – TWI Data Register TWAR – TWI (Slave) Address Register Using the TWI Transmission Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode Miscellaneous States Combining Several TWI Modes Multi-master Systems and Arbitration Analog Comparator SFIOR – Special Function IO Register ACSR – Analog Comparator Control and Status Register Analog Comparator Multiplexed Input Analog to Digital Converter Features Operation Starting a Conversion Prescaling and Conversion Timing Differential Gain Channels Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference ADC Noise Canceler Analog Input Circuitry Analog Noise Canceling Techniques Offset Compensation Schemes ADC Accuracy Definitions ADC Conversion Result ADMUX – ADC Multiplexer Selection Register ADCSRA – ADC Control and Status Register A ADCL and ADCH – The ADC Data Register ADCSRB – ADC Control and Status Register B JTAG Interface and On-chip Debug System Features Overview TAP – Test Access Port TAP Controller Using the Boundary -scan Chain Using the On-chip Debug system On-chip Debug Specific JTAG Instructions PRIVATE0; 0x8 PRIVATE1; 0x9 PRIVATE2; 0xA PRIVATE3; 0xB On-chip Debug Related Register in I/O Memory OCDR – On-chip Debug Register Using the JTAG Programming Capabilities Bibliography IEEE 1149.1 (JTAG) Boundary-scan Features System Overview Data Registers Bypass Register Device Identification Register Reset Register Boundary-scan Chain Boundary-scan Specific JTAG Instructions EXTEST; 0x0 IDCODE; 0x1 SAMPLE_PRELOAD; 0x2 AVR_RESET; 0xC BYPASS; 0xF Boundary-scan Related Register in I/O Memory MCUCSR – MCU Control and Status Register Boundary-scan Chain Scanning the Digital Port Pins Boundary-scan and the Two-wire Interface Scanning the RESET Pin Scanning the Clock Pins Scanning the Analog Comparator Scanning the ADC ATmega64 Boundary-scan Order Boundary-scan Description Language Files Boot Loader Support – Read- While-Write Self- programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read- While-Write Flash Sections RWW – Read-While- Write Section NRWW – No Read- While-Write Section Boot Loader Lock Bits Entering the Boot Loader Program SPMCSR – Store Program Memory Control Register Addressing the Flash During Self- programming Self-programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self-programming Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Simple Assembly Code Example for a Boot Loader ATmega64 Boot Loader Parameters Memory Programming Program and Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading SPI Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM SPI Serial Programming Characteristics Programming Via the JTAG Interface Programming Specific JTAG Instructions AVR_RESET (0xC) PROG_ENABLE (0x4) PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) PROG_PAGEREAD (0x7) Data Registers Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register Programming Algorithm Entering Programming Mode Leaving Programming Mode Performing Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuses Programming the Lock Bits Reading the Fuses and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Electrical Characteristics – TA = -40°C to 85°C Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Two-wire Serial Interface Characteristics SPI Timing Characteristics ADC Characteristics External Data Memory Timing Electrical Characteristics – TA = -40°C to 105°C Absolute Maximum Ratings* DC Characteristics Typical Characteristics – TA = -40°C to 85°C Active Supply Current Idle Supply Current Power-Down Supply Current Power-Save Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulse width ATmega64 Typical Characteristics – TA = -40°C to 105°C Active Supply Current Idle Supply Current Power-Down Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis Bod Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption Of Peripheral Units Current Consumption In Reset and Reset Pulse Width Register Summary Instruction Set Summary Ordering Information Packaging Information 64A 64M1 Errata ATmega64, rev. A to C, E Datasheet Revision History Changes from Rev. 2490Q-07/10 to Rev. 2490R-02/13 Changes from Rev. 2490P-07/09 to Rev. 2490Q-07/10 Changes from Rev. 2490O-08/08 to Rev. 2490P-07/09 Changes from Rev. 2490N-05/08 to Rev. 2490O-08/08 Changes from Rev. 2490M-08/07 to Rev. 2490N-05/08 Changes from Rev. 2490L-10/06 to Rev. 2490M-08/07 Changes from Rev. 2490K-04/06 to Rev. 2490L-10/06 Changes from Rev. 2490J-03/05 to Rev. 2490K-04/06 Changes from Rev. 2490I-10/04 to Rev. 2490J-03/05 Changes from Rev. 2490H-10/04 to Rev. 2490I-11/04 Changes from Rev. 2490G-03/04 to Rev. 2490H-10/04 Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03 Changes from Rev. 2490B-09/02 to Rev. 2490C-09/02 Changes from Rev. 2490A-10/01 to Rev. 2490B-09/02 Table of Contents