Datasheet AD7091 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 1 MSPS, Ultralow Power 12-Bit ADC in 8-Lead LFCSP |
| 页数 / 页 | 20 / 3 — Data Sheet. AD7091. SPECIFICATIONS. Table 1. Parameter. Test … |
| 修订版 | B |
| 文件格式/大小 | PDF / 469 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7091. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet AD7091 SPECIFICATIONS
VDD = 2.09 V to 5.25 V, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE1 fIN = 10 kHz sine wave Signal-to-Noise Ratio (SNR)2 VDD < 2.7 V 68 dB VDD ≥ 2.7 V 67 69 dB Signal-to-Noise-and-Distortion Ratio 66.3 68 dB (SINAD)2 Total Harmonic Distortion (THD)2 −86 −74 dB Spurious-Free Dynamic Range (SFDR)2 −85 −75 dB Aperture Delay2 5 ns Aperture Jitter2 40 ps Full Power Bandwidth2 At −3 dB 1.5 MHz At −0.1 dB 1.2 MHz DC ACCURACY Resolution 12 Bits Integral Nonlinearity (INL)2 ±0.6 ±1 LSB Differential Nonlinearity (DNL)2 Guaranteed no missing codes to 12 bits ±0.3 ±0.9 LSB Offset Error2 −8.5 ±0.7 +5 LSB Gain Error2 ±1.2 ±4 LSB Total Unadjusted Error (TUE)2 1.1 LSB ANALOG INPUT Input Voltage Range 0 VDD V DC Leakage Current ±1 µA Input Capacitance3 During acquisition phase 7 pF Outside acquisition phase 1 pF LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDD V Input Low Voltage (VINL) 0.3 × VDD V Input Current (IIN) Typically 10 nA, VIN = 0 V or VDD ±1 µA Input Capacitance (CIN)3 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 200 µA VDD − 0.2 V Output Low Voltage (VOL) ISINK = 200 µA 0.4 V Floating State Leakage Current ±1 µA Floating State Output Capacitance3 5 pF Output Coding Straight binary CONVERSION RATE Conversion Time 650 ns Track-and-Hold Acquisition Time2, 3 Full-scale step input 350 ns Throughput Rate 1 MSPS POWER REQUIREMENTS VDD 2.09 5.25 V IDD VIN = 0 V Normal Mode—Static4 VDD = 5.25 V 9.3 27 µA VDD = 3 V 9.1 28 µA Normal Mode—Operational VDD = 5.25 V, fSAMPLE = 1 MSPS 450 554 µA VDD = 3 V, fSAMPLE = 1 MSPS 367 442 µA VDD = 3 V, fSAMPLE = 100 kSPS 45 µA Power-Down Mode VDD = 5.25 V 0.374 8.2 µA Rev. B | Page 3 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7091 SPECIFICATIONS
VDD = 2.09 V to 5.25 V, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE1 fIN = 10 kHz sine wave Signal-to-Noise Ratio (SNR)2 VDD < 2.7 V 68 dB VDD ≥ 2.7 V 67 69 dB Signal-to-Noise-and-Distortion Ratio 66.3 68 dB (SINAD)2 Total Harmonic Distortion (THD)2 −86 −74 dB Spurious-Free Dynamic Range (SFDR)2 −85 −75 dB Aperture Delay2 5 ns Aperture Jitter2 40 ps Full Power Bandwidth2 At −3 dB 1.5 MHz At −0.1 dB 1.2 MHz DC ACCURACY Resolution 12 Bits Integral Nonlinearity (INL)2 ±0.6 ±1 LSB Differential Nonlinearity (DNL)2 Guaranteed no missing codes to 12 bits ±0.3 ±0.9 LSB Offset Error2 −8.5 ±0.7 +5 LSB Gain Error2 ±1.2 ±4 LSB Total Unadjusted Error (TUE)2 1.1 LSB ANALOG INPUT Input Voltage Range 0 VDD V DC Leakage Current ±1 µA Input Capacitance3 During acquisition phase 7 pF Outside acquisition phase 1 pF LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDD V Input Low Voltage (VINL) 0.3 × VDD V Input Current (IIN) Typically 10 nA, VIN = 0 V or VDD ±1 µA Input Capacitance (CIN)3 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 200 µA VDD − 0.2 V Output Low Voltage (VOL) ISINK = 200 µA 0.4 V Floating State Leakage Current ±1 µA Floating State Output Capacitance3 5 pF Output Coding Straight binary CONVERSION RATE Conversion Time 650 ns Track-and-Hold Acquisition Time2, 3 Full-scale step input 350 ns Throughput Rate 1 MSPS POWER REQUIREMENTS VDD 2.09 5.25 V IDD VIN = 0 V Normal Mode—Static4 VDD = 5.25 V 9.3 27 µA VDD = 3 V 9.1 28 µA Normal Mode—Operational VDD = 5.25 V, fSAMPLE = 1 MSPS 450 554 µA VDD = 3 V, fSAMPLE = 1 MSPS 367 442 µA VDD = 3 V, fSAMPLE = 100 kSPS 45 µA Power-Down Mode VDD = 5.25 V 0.374 8.2 µA Rev. B | Page 3 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE