Datasheet ADP5300 (Analog Devices) - 4

ADP5300 Data Sheet SPECIFICATIONS
VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.15 6.50 V SHUTDOWN CURRENT ISHUTDOWN 18 40 nA VEN = 0 V, −40°C ≤ TJ ≤ +85°C 18 130 nA VEN = 0 V, −40°C ≤ TJ ≤ +125°C QUIESCENT CURRENT Operating Quiescent Current in IQ_HYS 180 260 nA −40°C ≤ TJ ≤ +85°C Hysteresis Mode 180 350 nA −40°C ≤ TJ ≤ +125°C 570 1400 nA 100% duty cycle operation, VIN = 3.0 V, VOUT set to 3.3 V Operating Quiescent Current in IQ-HYS2 2.3 3.2 μA VIN = 3.6 V, VSTOP = 3.6 V Hysteresis Mode Operating Quiescent Current in PWM IQ_PWM 425 630 μA Mode UNDERVOLTAGE LOCKOUT UVLO UVLO Threshold Rising VUVLO_RISING 2.06 2.14 V Falling VUVLO_FALLING 1.90 2.00 V OSCILLATOR CIRCUIT Switching Frequency in PWM Mode fSW 1.7 2.0 2.3 MHz Feedback (FB) Threshold of Frequency VOSC_FOLD 0.3 V Fold SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNCCLOCK 1.5 2.5 MHz SYNC High Level Threshold SYNCHIGH 1.2 V SYNC Low Level Threshold SYNCLOW 0.4 V SYNC Duty Cycle Range SYNCDUTY 100 1/fSW − 150 ns SYNC/MODE Leakage Current ISYNC_LEAKAGE 50 150 nA VSYNC/MODE = 3.6 V MODE TRANSITION Transition Delay from Hysteresis Mode tHYS_TO_PWM 20 Clock cycles SYNC/MODE goes logic high to PWM Mode from logic low EN PIN Input Voltage Threshold High VIH 1.2 V Low VIL 0.4 V Input Leakage Current IEN_LEAKAGE 25 nA STOP Switching PWM Switching Stop Delay tSTOP-RISE-DELAY 10 ns STOP goes logic high from low PWM Switching Resume Delay tSTOP-FALL-DELAY 20 ns STOP goes logic low from high FB PIN Output Options by VID Resistor VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory options PWM Mode Fixed VID Code Voltage Accuracy VFB_PWM_FIX −0.6 +0.6 % TJ = 25°C, output voltage setting via factory fuse −1.2 +1.2 % −40°C ≤ TJ ≤ +125°C Adjustable VID Code Voltage VFB_PWM_ADJ −1.5 +1.5 % Output voltage setting via VID Accuracy resistor Rev. A | Page 4 of 21 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode Hysteresis Mode Mode Selection OSILLATOR AND SYNCHRONIZATION ADJUSTABLE AND FIXED OUTPUT VOLTAGES UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CURRENT LIMIT SHORT-CIRCUIT PROTECTION SOFT START STARTUP WITH PRECHARGED OUTPUT 100% DUTY OPERATION ACTIVE DISCHARGE VOUTOK FUNCTION STOP SWITCHING THERMAL SHUTDOWN APPLICATIONS INFORMATION EXTERNAL COMPONENT SELECTION SELECTING THE INDUCTOR OUTPUT CAPACITOR INPUT CAPACITOR EFFICIENCY Power Switch Conduction Losses Inductor Losses Driver Losses Transition Losses CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE