Datasheet CD4013B (Texas Instruments) - 3
| 制造商 | Texas Instruments |
| 描述 | CMOS Dual D-Type Flip-Flop |
| 页数 / 页 | 28 / 3 — CD4013B. www.ti.com. 5 Pin Configuration and Functions. D, J, N, NS, PW … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
CD4013B. www.ti.com. 5 Pin Configuration and Functions. D, J, N, NS, PW Package. 14-Pin SOIC, CDIP, PDIP, SO, TSSOP. Top View
文件文字版本
CD4013B www.ti.com
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions D, J, N, NS, PW Package 14-Pin SOIC, CDIP, PDIP, SO, TSSOP Top View
Q1 1 14 VDD Q1 2 13 Q2 CLOCK1 3 12 Q2 RESET1 4 11 CLOCK2 D1 5 10 RESET2 SET1 6 9 D2 VSS 7 8 SET2 Not to scale
Pin Functions PIN I/O DESCRIPTION NO. NAME
1 Q1 O Channel 1 output 2 Q1 O Inverted channel 1 output 3 CLOCK1 I Channel 1 clock input 4 RESET1 I Channel 1 reset 5 D1 I Channel 1 data input 6 SET1 I Channel 1 set 7 VSS — Ground 8 SET2 I Channel 2 set 9 D2 I Channel 2 data input 10 RESET2 I Channel 2 reset 11 CLOCK2 I Channel 2 clock input 12 Q2 O Inverted channel 2 output 13 Q2 O Channel 2 output 14 VDD — Power supply Copyright © 1998–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CD4013B Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Static 6.6 Electrical Characteristics: Dynamic 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions D, J, N, NS, PW Package 14-Pin SOIC, CDIP, PDIP, SO, TSSOP Top View
Q1 1 14 VDD Q1 2 13 Q2 CLOCK1 3 12 Q2 RESET1 4 11 CLOCK2 D1 5 10 RESET2 SET1 6 9 D2 VSS 7 8 SET2 Not to scale
Pin Functions PIN I/O DESCRIPTION NO. NAME
1 Q1 O Channel 1 output 2 Q1 O Inverted channel 1 output 3 CLOCK1 I Channel 1 clock input 4 RESET1 I Channel 1 reset 5 D1 I Channel 1 data input 6 SET1 I Channel 1 set 7 VSS — Ground 8 SET2 I Channel 2 set 9 D2 I Channel 2 data input 10 RESET2 I Channel 2 reset 11 CLOCK2 I Channel 2 clock input 12 Q2 O Inverted channel 2 output 13 Q2 O Channel 2 output 14 VDD — Power supply Copyright © 1998–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CD4013B Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Static 6.6 Electrical Characteristics: Dynamic 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information