Datasheet AD654 (Analog Devices) - 7

AD654
and insure the supply, source and load are appropriate. If provision between the various circuits in the system. Ceramic capacitors is made to trim offset, begin by setting the input to 1/10,000 of of 0.1 µF to 1.0 µF should be applied between the supply- full scale. Adjust the offset pot until the output is 1/10,000 of voltage pins and analog signal ground for proper bypassing on full scale (for example, 25 Hz for a FS of 250 kHz). This is most the AD654. A proper ground scheme appears in Figure 6. easily accomplished using a frequency meter connected to the output. The FS input should then be applied and the gain pot
10
V should be adjusted until the desired FS frequency is indicated.
CT 0.1
m
F INPUT PROTECTION 8 7 6 5
The AD654 was designed to be used with a minimum of additional
+5V
hardware. However, the successful application of a precision IC
RPU AD654 DIGITAL P.S.
involves a good understanding of possible pitfalls and the use of
GND
suitable precautions. Thus +VIN and RT pins should not be driven
1 2 3 4
more than 300 mV below –VS. Likewise, Logic Common should not drop more than 500 mV below –V
fOUT
S. This would cause inter-
RT
nal junctions to conduct, possibly damaging the IC. In addition
AGND
to the diode shown in Figures 1 and 2 protecting Logic Common,
VIN
a second Schottky diode (MBD101) can protect the AD654’s inputs from “below –V Figure 6. Proper Ground Scheme S’’ inputs as shown in Figure 5. It is also desirable not to drive +VIN and RT above +VS. In operation, the converter will exhibit a zero output for inputs above (+V
OUTPUT INTERFACING CONSIDERATION
S – 3.5 V). Also, control currents above 2 mA will increase nonlinearity. The output stage’s design allows easy interfacing to all digital logic families. The output NPN transistor’s emitter and collector are The AD654’s 80 dB dynamic range guarantees operation from a both uncommitted. The emitter can be tied to any voltage between control current of 1 mA (nominal FS) down to 100 nA (equiva- –V lent to 1 mV to 10 V FS). Below 100 nA improper operation of S and 4 volts below +VS, and the open collector can be pulled up to a voltage 36 volts above the emitter regardless of +V the oscillator may result, causing a false indication of input S. The high power output stage can sink over 10 mA at a maximum amplitude. In many cases this might be due to short-lived noise saturation voltage of 0.4 V. The stage limits the output current spikes which become added to input. For example, when scaled at 25 mA and can handle this limit indefinitely without damag- to accept an FS input of 1 V, the –80 dB level is only 100 µV, so ing the device. when the mean input is only 60 dB below FS (1 mV), noise spikes of 0.9 mV are sufficient to cause momentary malfunction.
NONLINEARITY SPECIFICATION
This effect can be minimized by using a simple low-pass filter The preferred method of specifying nonlinearity error is in terms ahead of the converter or a guard ring around the R of maximum deviation from the ideal relationship after calibrat- T pin. The filter can be assembled using the bias current compensation ing the converter at full scale. This error will vary with the full resistor discussed in the previous section. For an FS of 10 kHz, scale frequency and the mode of operation. The AD654 operates a single-pole filter with a time constant of 100 ms will be suitable, best at a 150 kHz full-scale frequency with a negative voltage input; but the optimum configuration will depend on the application the linearity is typically within 0.05%. Operating at higher fre- and the type of signal processing. Noise spikes are only likely to quencies or with positive inputs will degrade the linearity as be a cause of error when the input current remains near its mini- indicated in the Specifications Table. Typical linearity at various mum value for long periods of time; above 100 nA full integration temperatures is shown in Figure 7. of additive input noise occurs. Like the inputs, the capacitor terminals are sensitive to interference from other signals. The
10
timing capacitor should be located as close as possible to the
5
AD654 to minimize signal pickup in the leads. In some cases,
fAMB = –40
8
C
guard rings or shielding may be required.
1 AD654 0.5 fAMB = 0
8
C TO +85
8
C IIN 0.10 0.05 MAXIMUM NONLINEARITY – % MBD101 0.01 10 150 250 350 500
Figure 5. Input Protection
FULL-SCALE FREQUENCY – kHz DECOUPLING
Figure 7. Typical Nonlinearities at Different Full-Scale It is good engineering practice to use bypass capacitors on the Frequencies supply-voltage pins and to insert small-valued resistors (10 to 100 Ω) in the supply lines to provide a measure of decoupling –6– REV. C