Datasheet ATtiny13A. Summary (Microchip) - 5
| 制造商 | Microchip |
| 描述 | 8-bit AVR Microcontroller with 1K Bytes In-System Programmable Flash |
| 页数 / 页 | 20 / 5 — ATtiny13A |
| 文件格式/大小 | PDF / 591 Kb |
| 文件语言 | 英语 |
ATtiny13A
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ATtiny13A
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg- isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4- channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft- ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Inter- rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
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8126FS–AVR–05/12 Document Outline Features 1. Pin Configurations 1.1 Pin Description 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 7. Packaging Information 7.1 8P3 7.2 8S2 7.3 8S1 7.4 20M1 7.5 10M1 8. Errata 8.1 ATtiny13A Rev. G – H 8.2 ATtiny13A Rev. E – F 8.3 ATtiny13 Rev. A – D 9. Datasheet Revision History 9.1 Rev. 8126F – 05/12 9.2 Rev. 8126E – 07/10 9.3 Rev. 8126D – 11/09 9.4 Rev. 8126C – 09/09 9.5 Rev. 8126B – 11/08 9.6 Rev. 8126A – 05/08
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg- isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4- channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft- ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Inter- rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
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8126FS–AVR–05/12 Document Outline Features 1. Pin Configurations 1.1 Pin Description 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 7. Packaging Information 7.1 8P3 7.2 8S2 7.3 8S1 7.4 20M1 7.5 10M1 8. Errata 8.1 ATtiny13A Rev. G – H 8.2 ATtiny13A Rev. E – F 8.3 ATtiny13 Rev. A – D 9. Datasheet Revision History 9.1 Rev. 8126F – 05/12 9.2 Rev. 8126E – 07/10 9.3 Rev. 8126D – 11/09 9.4 Rev. 8126C – 09/09 9.5 Rev. 8126B – 11/08 9.6 Rev. 8126A – 05/08