Datasheet LT1671 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 60ns, Low Power, Single Supply, Ground-Sensing Comparator |
| 页数 / 页 | 12 / 6 — TYPICAL PERFORMANCE CHARACTERISTICS. t +. PD Response Time to. tPD … |
| 文件格式/大小 | PDF / 214 Kb |
| 文件语言 | 英语 |
TYPICAL PERFORMANCE CHARACTERISTICS. t +. PD Response Time to. tPD Response Time to. 5mV Overdrive. PIN FUNCTIONS. V+ (Pin 1)
该数据表的模型线
文件文字版本
LT1671
W U TYPICAL PERFORMANCE CHARACTERISTICS t + – PD Response Time to tPD Response Time to 5mV Overdrive 5mV Overdrive
1.4V 1.4V 5mV 5mV +IN +IN – 95mV Q OUT – 95mV Q OUT 0V 0V VS = ±5V 20ns/DIV VS = ±5V 20ns/DIV VOD = 5mV 1671 G18 VOD = 5mV 1671 G19
U U U PIN FUNCTIONS V+ (Pin 1)
: Positive Supply Voltage. Normally 5V.
GND (Pin 6):
Ground.
+IN (Pin 2):
Noninverting Input.
Q OUT (Pin 7):
Noninverting Logic Output. This pin is high when +IN is above – IN and LATCH ENABLE is low.
–IN (Pin 3):
Inverting Input.
Q OUT (Pin 8):
Inverting Logic Output. This pin is low
V– (Pin 4):
Negative Supply Voltage. Normally either 0V when +IN is above – IN and LATCH ENABLE is low. or – 5V.
LATCH ENABLE (Pin 5):
Latch Control Pin. When high, the outputs remain in a latched condition, independent of the current state of the inputs.
W U W TI I G DIAGRA S
VOD LATCH ENABLE ∆VIN VIN t t SU H tPD VIN VOUT tPD 1671 TD01 VOUT 1671 TD02 6
W U TYPICAL PERFORMANCE CHARACTERISTICS t + – PD Response Time to tPD Response Time to 5mV Overdrive 5mV Overdrive
1.4V 1.4V 5mV 5mV +IN +IN – 95mV Q OUT – 95mV Q OUT 0V 0V VS = ±5V 20ns/DIV VS = ±5V 20ns/DIV VOD = 5mV 1671 G18 VOD = 5mV 1671 G19
U U U PIN FUNCTIONS V+ (Pin 1)
: Positive Supply Voltage. Normally 5V.
GND (Pin 6):
Ground.
+IN (Pin 2):
Noninverting Input.
Q OUT (Pin 7):
Noninverting Logic Output. This pin is high when +IN is above – IN and LATCH ENABLE is low.
–IN (Pin 3):
Inverting Input.
Q OUT (Pin 8):
Inverting Logic Output. This pin is low
V– (Pin 4):
Negative Supply Voltage. Normally either 0V when +IN is above – IN and LATCH ENABLE is low. or – 5V.
LATCH ENABLE (Pin 5):
Latch Control Pin. When high, the outputs remain in a latched condition, independent of the current state of the inputs.
W U W TI I G DIAGRA S
VOD LATCH ENABLE ∆VIN VIN t t SU H tPD VIN VOUT tPD 1671 TD01 VOUT 1671 TD02 6