Datasheet LT1711, LT1712 (Analog Devices) - 7

LT1711/LT1712
U U U PI FU CTIO S LT1712 – IN A (Pin 1):
Inverting Input of A Channel Comparator.
Q B (Pin 11):
Noninverting Output of B Channel
+ IN A (Pin 2):
Noninverting Input of A Channel Comparator. Comparator.
Q B (Pin 12):
Inverting Output of B Channel
V – (Pins 3, 6):
Negative Supply Voltage, Usually – 5V. Pins Comparator. 3 and 6 should be connected together externally.
Q A (Pin 13):
Inverting Output of A Channel
V + (Pins 4, 5):
Positive Supply Voltage, Usually 5V. Pins Comparator. 4 and 5 should be connected together externally.
Q A (Pin 14):
Noninverting Output of A Channel
+ IN B (Pin 7):
Noninverting Input of B Channel Comparator. Comparator.
GND (Pin 15):
Ground Supply Voltage of A Channel
– IN B (Pin 8):
Inverting Input of B Channel Comparator. Comparator, Usually 0V
LATCH ENABLE B (Pin 9):
Latch Enable Input of B Channel
LATCH ENABLE A (Pin 16):
Latch Enable Input of A Comparator. With a logic high, the B output is latched. Channel Comparator. With a logic high, the A output is latched.
GND (Pin 10):
Ground Supply Voltage of B Channel Comparator, Usually 0V.
U U W U APPLICATIO S I FOR ATIO Common Mode Considerations
differential input stage, the LT1711/LT1712 bias current flows into or out of the device depending upon the com- The LT1711/LT1712 are specified for a common mode mon mode level. The input circuit consists of an NPN pair range of – 5.1V to 5.1V on a ±5V supply, or a common and a PNP pair. For inputs near the negative rail, the NPN mode range of – 0.1V to 5.1V on a single 5V supply. A more pair is inactive, and the input bias current flows out of the general consideration is that the common mode range is device; for inputs near the positive rail, the PNP pair is from 100mV below the negative supply to 100mV above inactive, and these currents flow into the device. For inputs the positive supply, independent of the actual supply far enough away from the supply rails, the input bias voltage. The criteria for common mode limit is that the current will be some combination of the NPN and PNP bias output still responds correctly to a small differential input currents. As the differential input voltage increases, the signal. input current of each pair will increase for one of the inputs When either input signal falls outside the common mode and decrease for the other input. Large differential input limit, the internal PN diode formed with the substrate can voltages result in different input currents as the input turn on resulting in significant current flow through the stage enters various regions of operation. To reduce the die. Schottky clamp diodes between the inputs and the influence of these changing input currents on system supply rails speed up recovery from excessive overdrive operation, use a low source resistance. conditions by preventing these substrate diodes from turning on.
Latch Pin Dynamics
The internal latches of the LT1711/LT1712 comparators
Input Bias Current
retain the input data (output latched) when their respec- Input bias current is measured with the outputs held at tive latch pin goes high. The latch pin will float to a low 2.5V with a 5V supply voltage. As with any rail-to-rail state when disconnected, but it is better to ground the 7