Datasheet MCP6141, MCP6142, MCP6143, MCP6144 (Microchip) - 7

MCP6141/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low.
10% 12% 2396 Samples s 11% 234 Samples 9% es V Representative Lot CM = VSS 10% nc 8% nce VDD = 1.4V 9% V rre 7% rre CM = VSS u 8% TA = +85°C to +125°C ccu 6% 7% f O 5% 6% o of Occ 4% e 5% ge ta 3% 4% en entag 3% 2% rc 2% 1% e Perc P 1% 0% 0% -3 -2 -1 0 1 2 3 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V.
12% 16% 234 Samples 11% 2267 Samples es 14% Representative Lot ces T 10% A = -40°C to +85°C V nc VDD = 5.5V 9% CM = VSS 12% rren VCM = VSS u 8% curre 10% TA = +85°C to +125°C 7% Occ 6% f Oc 8% 5% e of 4% 6% tag tage o 3% n 4% cen 2% 1% erce Per 2% P 0% 0% -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage Drift (µV/°C) Input Offset Voltage Drift (µV/°C) FIGURE 2-2:
Input Offset Voltage Drift
FIGURE 2-5:
Input Offset Voltage Drift with TA = -40°C to +85°C. with TA = +85°C to +125°C and VDD = 5.5V.
1000 1000 V 800 DD = 1.4V V 800 DD = 5.5V V) 600 TA = +125°C µ 600 e (µV) T 400 TA = +85°C e ( A = +125°C g 400 TA = +85°C 200 200 0 0 et Voltag -200 et Volta -200 -400 T Offs -400 A = +25°C Offs T -600 A = -40°C T -600 A = +25°C Input -800 TA = -40°C Input -800 -1000 -1000 .4 .2 0 2 4 6 8 0 2 4 6 8 .5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. Common Mode Input Voltage with VDD = 5.5V. © 2009 Microchip Technology Inc. DS21668D-page 7 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 CS Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Stability FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. FIGURE 4-4: Noise Gain for Inverting Gain Configuration. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. 4.5 MCP6143 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-9: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-10: High Side Battery Current Sensor. FIGURE 4-11: Summing Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulation Tool 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information