Datasheet MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004 (Microchip) - 5
| 制造商 | Microchip |
| 描述 | The MCP6001 is a single general purpose op amp offering rail-to-rail input and output over the 1.8 to 6V operating range |
| 页数 / 页 | 42 / 5 — MCP6001/1R/1U/2/4. 1.1. Test Circuits. EQUATION 1-1:. MCP600X. FIGURE 1-1: |
| 文件格式/大小 | PDF / 794 Kb |
| 文件语言 | 英语 |
MCP6001/1R/1U/2/4. 1.1. Test Circuits. EQUATION 1-1:. MCP600X. FIGURE 1-1:
该数据表的模型线
- MCP6001RT-E/OT MCP6001RT-E/OTVAO MCP6001RT-I/OT MCP6001RT-I/OTVAO MCP6001T-E/LT MCP6001T-E/LTVAO MCP6001T-E/OT MCP6001T-E/OTVAO MCP6001T-I/LT MCP6001T-I/LTVAO MCP6001T-I/OT MCP6001T-I/OT-HCM MCP6001T-I/OTVAO MCP6001UT-E/OT MCP6001UT-E/OTVAO MCP6001UT-I/OT
- MCP6002-E/MC MCP6002-E/MCVAO MCP6002-E/MS MCP6002-E/MSVAO MCP6002-E/P MCP6002-E/SN MCP6002-E/SNVAO MCP6002-I/MS MCP6002-I/P MCP6002-I/SN MCP6002-I/SNVAO MCP6002T-E/MC MCP6002T-E/MCVAO MCP6002T-E/MS MCP6002T-E/MSVAO MCP6002T-E/SN MCP6002T-E/SNVAO MCP6002T-I/MS MCP6002T-I/MSVAO MCP6002T-I/SN MCP6002T-I/SNVAO
文件文字版本
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MCP6001/1R/1U/2/4 1.1 Test Circuits
C The circuit used for most DC and AC tests is shown in F 6.8 pF Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common mode voltage ((V R P + VM)/2), and that G RF VOST includes VOS plus the effects (on the input offset 100 kΩ 100 kΩ error, V V V OST) of temperature, CMRR, PSRR and AOL. P DD/2 VDD
EQUATION 1-1:
VIN+ C C B1 B2 G = R ⁄ R
MCP600X
DM F G 100 nF 1 µF V = (V + V ⁄ 2) ⁄ 2 CM P DD V = V – V VIN– OST IN– IN+ V = (V ⁄ 2) + (V – V ) + V (1 + G ) OUT DD P M OST DM V V M OUT R R C Where: G RF L L 100 kΩ 100 kΩ 10 kΩ 60 pF GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode (V) CF Input Voltage VL 6.8 pF VOST = Op Amp’s Total Input Offset (mV)
FIGURE 1-1:
AC and DC Test Circuit for Voltage Most Specifications. © 2009 Microchip Technology Inc. DS21733J-page 5 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
MCP6001/1R/1U/2/4 1.1 Test Circuits
C The circuit used for most DC and AC tests is shown in F 6.8 pF Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common mode voltage ((V R P + VM)/2), and that G RF VOST includes VOS plus the effects (on the input offset 100 kΩ 100 kΩ error, V V V OST) of temperature, CMRR, PSRR and AOL. P DD/2 VDD
EQUATION 1-1:
VIN+ C C B1 B2 G = R ⁄ R
MCP600X
DM F G 100 nF 1 µF V = (V + V ⁄ 2) ⁄ 2 CM P DD V = V – V VIN– OST IN– IN+ V = (V ⁄ 2) + (V – V ) + V (1 + G ) OUT DD P M OST DM V V M OUT R R C Where: G RF L L 100 kΩ 100 kΩ 10 kΩ 60 pF GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode (V) CF Input Voltage VL 6.8 pF VOST = Op Amp’s Total Input Offset (mV)
FIGURE 1-1:
AC and DC Test Circuit for Voltage Most Specifications. © 2009 Microchip Technology Inc. DS21733J-page 5 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information