Datasheet MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004 (Microchip) - 7

MCP6001/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, and CL = 60 pF.
20% 0
64,695 Samples
18%
VDD = 1.8V VCM = VSS
V) -100 16% µ 14% -200 12% -300 Occurrences 10% -400 8% set Voltage (
TA = -40°C
age of
T
6% -500
A = +25°C
Off
TA = +85°C
4% -600
TA = +125°C
2% Input Percent 0% -700 0 2 4 6 8 0 2 4 6 8 0 2 5 -4 -3 -2 -1 0 1 2 3 4 5 .4 .2 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. Input Offset Voltage (mV) Common Mode Input Voltage (V) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V.
18% 0 16%
2453 Samples
)
VDD = 5.5V TA = -40°C to +125°C
-100 14%
VCM = VSS
12% -200 age (µV 10% lt o -300 8% V 6% -400 age of Occurrences fset
TA = -40°C
4% -500
TA = +25°C
2%
TA = +85°C
-600
T
Percent 0% Input Of
A = +125°C
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -700 0 5 0 5 0 5 0 5 0 5 0 5 0 Input Offset Voltage Drift; .5 -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. TC1 (µV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V.
45% 200 40%
2453 Samples T
)
A = -40°C to +125°C
35% 150
VCM = VSS
30% 100 25% age (µV 50 lt
V
20% o
DD = 5.5V
15% V 0 age of Occurrences et
VDD = 1.8V
10% s -50 5% Off -100 0% Percent 0 1 2 3 4 5 6 7 -150 .02 .01 0 0 0 0 0 0 0 0 Input
VCM = VSS
-0 -0 0. 0. 0. 0. 0. 0. 0. 0. -200 Input Offset Quadratic Temp. Co.; 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TC2 (µV/°C2) Output Voltage (V) FIGURE 2-3:
Input Offset Quadratic
FIGURE 2-6:
Input Offset Voltage vs. Temp. Co. Output Voltage. © 2009 Microchip Technology Inc. DS21733J-page 7 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information