Datasheet MCP6271, MCP6271R, MCP6272, MCP6273, MCP6274, MCP6275 (Microchip)

MCP6271/1R/2/3/4/5 170 µA, 2 MHz Rail-to-Rail Op Amp Features Description
• Gain Bandwidth Product: 2 MHz (typical) The Microchip Technology Inc. MCP6271/1R/2/3/4/5 • Supply Current: IQ = 170 µA (typical) family of operational amplifiers (op amps) provide wide • Supply Voltage: 2.0V to 6.0V bandwidth for the current. This family has a 2 MHz • Rail-to-Rail Input/Output Gain Bandwidth Product (GBWP) and a 65° Phase Margin. This family also operates from a single supply • Extended Temperature Range: –40°C to +125°C voltage as low as 2.0V, while drawing 170 µA (typical) • Available in Single, Dual and Quad Packages quiescent current. The MCP6271/1R/2/3/4/5 supports • Parts with Chip Select (CS) rail-to-rail input and output swing, with a common mode - Single (
MCP6273
) input voltage range of VDD + 300 mV to VSS – 300 mV. - Dua l (
MCP6275
) This family of op amps is designed with Microchip’s advanced CMOS process.
Applications
The MCP6275 has a Chip Select input (CS) for dual op • Automotive amps in an 8-pin package and is manufactured by • Portable Equipment cascading two op amps (the output of op amp A • Photodiode Amplifier connected to the non-inverting input of op amp B). The CS input puts the device in low power mode. • Analog Filters • Notebooks and PDAs The MCP6271/1R/2/3/4/5 family operates over the Extended Temperature Range of –40°C to +125°C, • Battery Powered Systems with a power supply range of 2.0V to 6.0V.
Available Tools
• SPICE Macro Models • FilterLab® Software • Mindi™ Circuit Designer & Simulator • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes
Package Types MCP6271 MCP6271 MCP6271R MCP6272 PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP
NC 1 8 NC V 1 5 V V 1 5 V V 1 8 V OUT DD OUT SS OUTA DD V V 2 + V 2 + IN– 2 - 7 VDD V SS - DD - INA– 2 - + 7 VOUTB V 3 + 6 IN+ VOUT V 3 4 V 3 4 V 3 + - 6 IN+ VIN– IN+ VIN– INA+ VINB– V 4 5 NC SS V 4 5 V SS INB+
MCP6273 MCP6273 MCP6274 MCP6275 PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP
NC 1 8 CS V 1 6 V V 1 14 V OUT DD OUTA OUTD V 1 8 V OUTA/VINB+ DD V 2 - 7 V V 2 + 5 CS V 2 13 SS - + + - V V 2 - + IN– DD - INA– IND– INA– 7 VOUTB V 3 + 6 V V 3 4 V 3 12 V V 3 + - IN+ OUT IN+ VIN– INA+ IND+ 6 INA+ VINB– V 4 5 NC SS V 4 11 V DD SS V 4 5 CS SS V 5 10 INB+ VINC+ VINB– 6 - + + - 9 VINC– VOUTB 7 8 VOUTC © 2008 Microchip Technology Inc. DS21810F-page 1 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. FIGURE 2-8: Input Offset Voltage vs. Output Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-20: Input Noise Voltage Density vs. Frequency. FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-22: Slew Rate vs. Temperature. FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-26: Large Signal Non-inverting Pulse Response. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). FIGURE 2-29: Large Signal Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-32: Input Current vs. Input Voltage. FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6275’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP6273/5 Chip Select 4.5 Cascaded Dual Op Amps (MCP6275) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Unused Amplifiers FIGURE 4-6: Unused Op Amps. 4.7 Supply Bypass 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Active Full-wave Rectifier. FIGURE 4-9: Non-Inverting Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Integrator Circuit with Active Compensation. FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. 5.0 Design Tools 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information