Datasheet MCP6271, MCP6271R, MCP6272, MCP6273, MCP6274, MCP6275 (Microchip) - 10

MCP6271/1R/2/3/4/5 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
250 700 V VDD = 5.5V DD = 2.0V Op Amp turns Off 600 Hysteresis 200 t nt Op Amp turns On r) 500 rre r) rren e u CS swept ifie 150 ifi 400 Low-to-High t Cu t C pl en Hysteresis m ampl t 100 cen /a 300 p Op Amp A/ -Low iesc turns (µ CS swept CS swept ies u (µA 200 -to Qu h On/Off 50 High-to-Low Low-to-High Q ig 100 CS swe H 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-25:
Quiescent Current vs. Chip
FIGURE 2-28:
Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). and MCP6275 only).
5.0 5.0 G = -1 V/V 4.5 G = +1 V/V 4.5 V VDD = 5.0V 4.0 DD = 5.0V 4.0 ) 3.5 (V 3.5 e (V) e g 3.0 3.0 tag 2.5 2.5 Vol 2.0 2.0 ut put Volta 1.5 tp 1.5 Out Ou 1.0 1.0 0.5 0.5 0.0 0.0 Time (5 µs/div) Time (5 µs/div) FIGURE 2-26:
Large Signal Non-inverting
FIGURE 2-29:
Large Signal Inverting Pulse Pulse Response. Response.
G = +1 V/V G = -1 V/V ) ) iv iv /d /d V V 0 m 0 m 1 e (1 e ( ltag tag o Vol ut V ut tp tp u O Ou Time (2 µs/div) Time (2 µs/div) FIGURE 2-27:
Small Signal Non-inverting
FIGURE 2-30:
Small Signal Inverting Pulse Pulse Response. Response. DS21810F-page 10 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. FIGURE 2-8: Input Offset Voltage vs. Output Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-20: Input Noise Voltage Density vs. Frequency. FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-22: Slew Rate vs. Temperature. FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-26: Large Signal Non-inverting Pulse Response. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). FIGURE 2-29: Large Signal Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-32: Input Current vs. Input Voltage. FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6275’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP6273/5 Chip Select 4.5 Cascaded Dual Op Amps (MCP6275) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Unused Amplifiers FIGURE 4-6: Unused Op Amps. 4.7 Supply Bypass 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Active Full-wave Rectifier. FIGURE 4-9: Non-Inverting Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Integrator Circuit with Active Compensation. FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. 5.0 Design Tools 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information