Datasheet ADA4075-2 (Analog Devices) - 8

Data Sheet ADA4075-2 40 40 VSY = ±15V VSY = ±5V V V 35 CM = 0V 35 CM = 0V BASED ON 300 OP AMPS BASED ON 300 OP AMPS LFCSP PACKAGE LFCSP PACKAGE 30 30 RS RS IE IE IF 25 IF L 25 L P P AM 20 AM F 20 F R O R O 15 15 BE BE NUM 10 NUM 10 5 5 0 0 0 1 2 3 4 5 6 7 8
043
0 1 2 3 4 5 6 7 8
052
TCVOS (µV/°C)
07642-
TCVOS (µV/°C)
07642- Figure 9. Input Offset Voltage Drift Distribution Figure 12. Input Offset Voltage Drift Distribution
300 300 VSY = ±15V VSY = ±5V BASED ON 60 OP AMPS BASED ON 60 OP AMPS 200 200 100 100 V) V) (μ 0 (μ 0 OSV OSV –100 –100 –200 –200 –300 –300 –15 –10 –5 0 5 10 15
005
–5 –4 –3 –2 –1 0 1 2 3 4 5
008
VCM (V) V
07642-
CM (V)
07642- Figure 10. Input Offset Voltage vs. Common-Mode Voltage Figure 13. Input Offset Voltage vs. Common-Mode Voltage
80 100 VSY = ±15V VSY = ±5V 80 60 60 A) A) n n ( 40 ( I B I B 40 20 20 0 0 –50 –25 0 25 50 75 100 125
009
–50 –25 0 25 50 75 100 125
012
TEMPERATURE (°C) TEMPERATURE (°C)
07642- 07642- Figure 11. Input Bias Current vs. Temperature Figure 14. Input Bias Current vs. Temperature Rev. C | Page 7 of 24 Document Outline Features Applications Pin Configurations General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance Power Sequencing ESD Caution Typical Performance Characteristics Applications Information Input Protection Total Harmonic Distortion Phase Reversal DAC Output Filter Balanced Line Driver Balanced Line Receiver Low Noise Parametric Equalizer Schematic Outline Dimensions Ordering Guide