Datasheet LTC1090 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Single Chip 10-Bit Data Acquisition System |
| 页数 / 页 | 28 / 6 — PI FU CTIO S. PIN. FUNCTION. DESCRIPTION. BLOCK DIAGRA |
| 文件格式/大小 | PDF / 356 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. PIN. FUNCTION. DESCRIPTION. BLOCK DIAGRA
该数据表的模型线
文件文字版本
LTC1090
U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION
1-8 CH0 to CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND. 9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is usually tied to the analog ground plane. 10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane. 11 AGND Analog Ground AGND should be tied directly to the analog ground plane. 12 V – Negative Supply Tie V– to most negative potential in the circuit. (Ground in single supply applications.) 13,14 REF –, REF+ Reference Inputs The reference inputs must be kept free of noise with respect to AGND. 15 CS Chip Select Input A logic low on this input enables data transfer. 16 DOUT Digital Data Output The A/D conversion result is shifted out of this output. 17 DIN Data Input The A/D configuration word is shifted into this input. 18 SCLK Shift Clock This clock synchronizes the serial data transfer. 19 ACLK A/D Conversion Clock This clock controls the A/D conversion process. 20 VCC Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
W BLOCK DIAGRA
20 18 V SCLK CC 17 INPUT SHIFT OUTPUT 16 D SHIFT IN D REGISTER OUT REGISTER 1 SAMPLE CH0 2 AND HOLD CH1 COMP 3 CH2 4 10-BIT CH3 ANALOG 5 SAR INPUT CH4 6 MUX CH5 10-BIT 7 CH6 CAPACITIVE 8 CH7 DAC 9 COM 19 ACLK 10 11 12 13 14 CONTROL 15 DGND AGND REF – REF+ V– AND CS TIMING LTC1090 • BD01 1090fc 6
U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION
1-8 CH0 to CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND. 9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is usually tied to the analog ground plane. 10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane. 11 AGND Analog Ground AGND should be tied directly to the analog ground plane. 12 V – Negative Supply Tie V– to most negative potential in the circuit. (Ground in single supply applications.) 13,14 REF –, REF+ Reference Inputs The reference inputs must be kept free of noise with respect to AGND. 15 CS Chip Select Input A logic low on this input enables data transfer. 16 DOUT Digital Data Output The A/D conversion result is shifted out of this output. 17 DIN Data Input The A/D configuration word is shifted into this input. 18 SCLK Shift Clock This clock synchronizes the serial data transfer. 19 ACLK A/D Conversion Clock This clock controls the A/D conversion process. 20 VCC Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
W BLOCK DIAGRA
20 18 V SCLK CC 17 INPUT SHIFT OUTPUT 16 D SHIFT IN D REGISTER OUT REGISTER 1 SAMPLE CH0 2 AND HOLD CH1 COMP 3 CH2 4 10-BIT CH3 ANALOG 5 SAR INPUT CH4 6 MUX CH5 10-BIT 7 CH6 CAPACITIVE 8 CH7 DAC 9 COM 19 ACLK 10 11 12 13 14 CONTROL 15 DGND AGND REF – REF+ V– AND CS TIMING LTC1090 • BD01 1090fc 6