Datasheet LTC1604 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown |
| 页数 / 页 | 20 / 9 — APPLICATIONS INFORMATION. Figure 2a. Nap Mode to Sleep Mode Timing. … |
| 文件格式/大小 | PDF / 586 Kb |
| 文件语言 | 英语 |
APPLICATIONS INFORMATION. Figure 2a. Nap Mode to Sleep Mode Timing. Figure 2b. SHDN to CONVST Wake-Up Timing
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LTC1604
APPLICATIONS INFORMATION
currents are shut down and only leakage current remains SHDN (about 1μA). Wake-up time from Sleep mode is much t3 slower since the reference circuit must power up and CS settle. Sleep mode wake-up time is dependent on the value 1604 F02a of the capacitor connected to the REFCOMP (Pin 4). The
Figure 2a. Nap Mode to Sleep Mode Timing
wake-up time is 160ms with the recommended 47μF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in SHDN shutdown when SHDN is low. The shutdown mode is t4 selected with Pin 32 (CS). When SHDN is low, CS low CONVST selects nap and CS high selects sleep. 1604 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing Timing and Control
Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge CS applied to the CONVST pin will start a conversion after the t2 ADC has been selected (i.e., CS is low). Once initiated, CONVST it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY t1 is low during a conversion. RD 1604 F03 We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in
Figure 3. CS top CONVST Setup Timing
Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upset- 4 ting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, 3 if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. 2 tCONV tACQ Similarly, if CONVST returns high after the conversion is over(e.g., CONVST low time >tCONV), accuracy is unaf- CHANGE IN DNL (LSB) 1 fected. For best results, keep t5 less than 500ns or greater than tCONV. 0 Figures 5 through 9 show several different modes of op- 0 400 800 1200 1600 2000 2400 2800 CONVST LOW TIME, t5 (ns) eration. In modes 1a and 1b (Figures 5 and 6), CS and RD 1604 F04 are both tied low. The falling edge of CONVST starts the
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
conversion. The data outputs are always enabled and data
CONVST Pulse Returns High Early in the Conversion or After
can be latched with the BUSY rising edge. Mode 1a shows
the End of Conversion
operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are 1604fa 9
APPLICATIONS INFORMATION
currents are shut down and only leakage current remains SHDN (about 1μA). Wake-up time from Sleep mode is much t3 slower since the reference circuit must power up and CS settle. Sleep mode wake-up time is dependent on the value 1604 F02a of the capacitor connected to the REFCOMP (Pin 4). The
Figure 2a. Nap Mode to Sleep Mode Timing
wake-up time is 160ms with the recommended 47μF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in SHDN shutdown when SHDN is low. The shutdown mode is t4 selected with Pin 32 (CS). When SHDN is low, CS low CONVST selects nap and CS high selects sleep. 1604 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing Timing and Control
Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge CS applied to the CONVST pin will start a conversion after the t2 ADC has been selected (i.e., CS is low). Once initiated, CONVST it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY t1 is low during a conversion. RD 1604 F03 We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in
Figure 3. CS top CONVST Setup Timing
Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upset- 4 ting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, 3 if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. 2 tCONV tACQ Similarly, if CONVST returns high after the conversion is over(e.g., CONVST low time >tCONV), accuracy is unaf- CHANGE IN DNL (LSB) 1 fected. For best results, keep t5 less than 500ns or greater than tCONV. 0 Figures 5 through 9 show several different modes of op- 0 400 800 1200 1600 2000 2400 2800 CONVST LOW TIME, t5 (ns) eration. In modes 1a and 1b (Figures 5 and 6), CS and RD 1604 F04 are both tied low. The falling edge of CONVST starts the
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
conversion. The data outputs are always enabled and data
CONVST Pulse Returns High Early in the Conversion or After
can be latched with the BUSY rising edge. Mode 1a shows
the End of Conversion
operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are 1604fa 9