Datasheet LTC1606 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 250ksps, Single Supply ADC |
| 页数 / 页 | 16 / 8 — TEST CIRCUITS. Load Circuit for Access Timing. Load Circuit for Output … |
| 文件格式/大小 | PDF / 205 Kb |
| 文件语言 | 英语 |
TEST CIRCUITS. Load Circuit for Access Timing. Load Circuit for Output Float Delay. APPLICATIO S I FOR ATIO. Conversion Details
该数据表的模型线
- LTC1606ACG#PBF LTC1606ACG#PBF LTC1606ACG#TRPBF LTC1606ACG#TRPBF LTC1606ACSW#PBF LTC1606ACSW#PBF LTC1606ACSW#TRPBF LTC1606ACSW#TRPBF LTC1606AIG#PBF LTC1606AIG#PBF LTC1606AIG#TRPBF LTC1606AIG#TRPBF LTC1606AISW#PBF LTC1606AISW#PBF LTC1606AISW#TRPBF LTC1606AISW#TRPBF LTC1606CG#PBF LTC1606CG#PBF LTC1606CG#TRPBF LTC1606CG#TRPBF LTC1606CSW#PBF LTC1606CSW#PBF LTC1606CSW#TRPBF LTC1606CSW#TRPBF LTC1606IG#PBF LTC1606IG#PBF LTC1606IG#TRMPBF LTC1606IG#TRPBF LTC1606IG#TRPBF LTC1606ISW#PBF LTC1606ISW#PBF LTC1606ISW#TRPBF LTC1606ISW#TRPBF
文件文字版本
LTC1606
TEST CIRCUITS Load Circuit for Access Timing Load Circuit for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k 30pF 30pF 1k 30pF 30pF 1606 TC01 1606 TC02 A. Hi-Z TO VOH AND VOL TO VOH B. Hi-Z TO VOL AND VOH TO VOL A. VOH TO Hi-Z B. VOL TO Hi-Z
U U W U APPLICATIO S I FOR ATIO Conversion Details
the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. The LTC1606 uses a successive approximation algorithm In this acquire phase, a minimum delay of 1.5µs will and an internal sample-and-hold circuit to convert an provide enough time for the sample-and-hold capacitor to analog signal to a 16-bit or two byte parallel output. The acquire the analog signal. During the convert phase, the ADC is complete with a precision reference and an internal autozero switches open, putting the comparator into the clock. The control logic provides easy interface to micro- compare mode. The input switch switches C processors and DSPs. (Please refer to the Digital Interface SAMPLE to ground, injecting the analog input charge onto the sum- section for the data format.) ming junction. This input charge is successively com- Conversion start is controlled by the CS and R/C inputs. At pared with the binary-weighted charges supplied by the the start of conversion, the successive approximation capacitive DAC. Bit decisions are made by the high speed register (SAR) is reset. Once a conversion cycle has comparator. At the end of a conversion, the DAC output begun, it cannot be restarted. balances the VIN input charge. The SAR contents (a 16-bit During the conversion, the internal 16-bit capacitive DAC data word) that represents the VIN are loaded into the output is sequenced by the SAR from the most significant 16-bit output latches. bit (MSB) to the least significant bit (LSB). Referring to
Driving the Analog Inputs
Figure 1, VIN is connected through the resistor divider to The nominal input range for the LTC1606 is ±10V or SAMPLE (±4 • VREF) and the input is overvoltage protected to ±25V. The input impedance is typically 10k SI Ω, therefore, it should C RIN1 SAMPLE SAMPLE be driven with a low impedance source. Wideband noise VIN – coupling into the input can be minimized by placing a HOLD RIN2 1000pF capacitor at the input as shown in Figure 2. An + CDAC COMPARATOR NPO-type capacitor gives the lowest distortion. Place the DAC VDAC S A 200Ω R AIN VIN 1000pF 33.2k LTC1606 16-BIT CAP LATCH 1606 • F01 1606 • F02
Figure 1. LTC1606 Simplified Equivalent Circuit Figure 2. Analog Input Filtering
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TEST CIRCUITS Load Circuit for Access Timing Load Circuit for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k 30pF 30pF 1k 30pF 30pF 1606 TC01 1606 TC02 A. Hi-Z TO VOH AND VOL TO VOH B. Hi-Z TO VOL AND VOH TO VOL A. VOH TO Hi-Z B. VOL TO Hi-Z
U U W U APPLICATIO S I FOR ATIO Conversion Details
the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. The LTC1606 uses a successive approximation algorithm In this acquire phase, a minimum delay of 1.5µs will and an internal sample-and-hold circuit to convert an provide enough time for the sample-and-hold capacitor to analog signal to a 16-bit or two byte parallel output. The acquire the analog signal. During the convert phase, the ADC is complete with a precision reference and an internal autozero switches open, putting the comparator into the clock. The control logic provides easy interface to micro- compare mode. The input switch switches C processors and DSPs. (Please refer to the Digital Interface SAMPLE to ground, injecting the analog input charge onto the sum- section for the data format.) ming junction. This input charge is successively com- Conversion start is controlled by the CS and R/C inputs. At pared with the binary-weighted charges supplied by the the start of conversion, the successive approximation capacitive DAC. Bit decisions are made by the high speed register (SAR) is reset. Once a conversion cycle has comparator. At the end of a conversion, the DAC output begun, it cannot be restarted. balances the VIN input charge. The SAR contents (a 16-bit During the conversion, the internal 16-bit capacitive DAC data word) that represents the VIN are loaded into the output is sequenced by the SAR from the most significant 16-bit output latches. bit (MSB) to the least significant bit (LSB). Referring to
Driving the Analog Inputs
Figure 1, VIN is connected through the resistor divider to The nominal input range for the LTC1606 is ±10V or SAMPLE (±4 • VREF) and the input is overvoltage protected to ±25V. The input impedance is typically 10k SI Ω, therefore, it should C RIN1 SAMPLE SAMPLE be driven with a low impedance source. Wideband noise VIN – coupling into the input can be minimized by placing a HOLD RIN2 1000pF capacitor at the input as shown in Figure 2. An + CDAC COMPARATOR NPO-type capacitor gives the lowest distortion. Place the DAC VDAC S A 200Ω R AIN VIN 1000pF 33.2k LTC1606 16-BIT CAP LATCH 1606 • F01 1606 • F02
Figure 1. LTC1606 Simplified Equivalent Circuit Figure 2. Analog Input Filtering
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