Datasheet LTC1852, LTC1853 (Analog Devices) - 8

LTC1852/LTC1853
PIN FUNCTIONS D9/S0 (Pin 23, LTC1853):
Three-State Digital Data Outputs.
UNI/BIP (Pin 38):
Unipolar/Bipolar Select Input. Logic low Active when RD is low. Following a conversion, bit 9 of the selects a unipolar input span, a high logic level selects a present conversion is available on this pin. In Readback bipolar input span. mode, the end of sequence bit of the current sequencer
A0 to A2 (Pins 39 to 41):
MUX Address Input Pins. location (S0) is available on this pin. The output swings between OV
DIFF (Pin 42):
Single-Ended/Differential Select Input. DD and OGND. A low logic level selects single ended, a high logic level
D6 to D0 (Pins 24 to 30, LTC1852):
Three-State Digital selects differential. Data Outputs. Active when RD is low. The outputs swing between OV
WR (Pin 43):
Write Input. In Direct Address mode, WR DD and OGND. low enables the MUX address and confi guration input pins
D8 to D0 (Pins 24 to 32, LTC1853):
Three-State Digital (Pins 37 to 42). WR can be tied low or the rising edge of Data Outputs. Active when RD is low. The outputs swing WR can be used to latch the data. In Program mode, WR between OVDD and OGND. is used to program the sequencer. WR low enables the
NC (Pins 31 to 32, LTC1852):
No Connect. There is no MUX address and confi guration input pins (Pins 37 to 42). internal connection to these pins. The rising edge of WR latches the data and increments
BUSY
the counter to the next sequencer location.
(Pin 33):
Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will
RD (Pin 44):
Read Input. During normal operation, RD go low and remain low until the conversion is completed. enables the output drivers when CS is low. In Readback The rising edge may be used to latch the output data. mode (M1 high, M0 low), RD going low reads the cur- BUSY will also go low while the part is in Program/Read- rent sequencer location, RD high advances to the next back mode (M1 high, M0 low) and remain low until M0 sequencer location. is brought back high. The output swings between OVDD
CONVST (Pin 45):
Conversion Start Input. This active low and OGND. signal starts a conversion on its falling edge.
OGND (Pin 34):
Digital Data Output Ground. Tie to analog
CS (Pin 46):
Chip Select Input. The chip select input must ground plane. May be tied to logic ground if desired. be low for the ADC to recognize the CONVST and RD inputs.
OVDD (Pin 35):
Digital Data Output Supply. Normally tied If SHDN is low, a low logic level on CS selects Nap mode; to 5V, can be used to interface with 3V digital logic. Bypass a high logic level on CS selects Sleep mode. to OGND with 10μF tantalum in parallel with 0.1μF ceramic
SHDN (Pin 47):
Power Shutdown Input. A low logic level or 10μF ceramic. will invoke the Shutdown mode selected by the CS pin.
M0 (Pin 36):
Mode Select Pin 0. Used in conjunction with CS low selects Nap mode, CS high selects Sleep mode. M1 to select operating mode. See Table 5. Tie high if unused.
PGA (Pin 37):
Gain Select Input. A high logic level selects
M1 (Pin 48):
Mode Select Pin 1. Used in conjunction with gain = 1, a low logic level selects gain = 2. M0 to select operating mode. See Table 5. 18523fa 8