Datasheet LTC2172-14, LTC2171-14, LTC2170-14 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 65Msps Low Power Quad ADCs |
| 页数 / 页 | 34 / 6 — p ower requireMenTs The. denotes the specifications which apply over the … |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
p ower requireMenTs The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
- LTC2170CUKG-14#PBF LTC2170CUKG-14#PBF LTC2170CUKG-14#TRPBF LTC2170CUKG-14#TRPBF LTC2170IUKG-14#PBF LTC2170IUKG-14#PBF LTC2170IUKG-14#TRPBF LTC2170IUKG-14#TRPBF
文件文字版本
LTC2172-14/ LTC2171-14/LTC2170-14
p ower requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2172-14 LTC2171-14 LTC2170-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 157 181 96 112 75 85 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 16 16 15 mA 1-Lane Mode, 3.5mA Mode 30 29 28 mA 2-Lane Mode, 1.75mA Mode l 25 29 24 27 24 27 mA 2-Lane Mode, 3.5mA Mode l 47 52 46 51 45 50 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 311 202 162 mW 1-Lane Mode, 3.5mA Mode 337 225 185 mW 2-Lane Mode, 1.75mA Mode l 328 378 216 250 178 202 mW 2-Lane Mode, 3.5mA Mode l 367 419 256 293 216 243 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 75 75 75 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
Ti Ming characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2172-14 LTC2171-14 LTC2170-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 21721014fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
p ower requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2172-14 LTC2171-14 LTC2170-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 157 181 96 112 75 85 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 16 16 15 mA 1-Lane Mode, 3.5mA Mode 30 29 28 mA 2-Lane Mode, 1.75mA Mode l 25 29 24 27 24 27 mA 2-Lane Mode, 3.5mA Mode l 47 52 46 51 45 50 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 311 202 162 mW 1-Lane Mode, 3.5mA Mode 337 225 185 mW 2-Lane Mode, 1.75mA Mode l 328 378 216 250 178 202 mW 2-Lane Mode, 3.5mA Mode l 367 419 256 293 216 243 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 75 75 75 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
Ti Ming characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2172-14 LTC2171-14 LTC2170-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 21721014fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts