LTC2182/LTC2181/LTC2180 POWER REQUIREMENTSThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 9)LTC2182LTC2181LTC2180SYMBOL PARAMETERCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSCMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 89 99 64 72 43.5 50 mA Sine Wave Input 91 66 44.5 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 5 3 2 mA PDISS Power Dissipation DC Input l 160 179 115 130 78.3 90 mW Sine Wave Input, OVDD = 1.2V 170 122 82.5 mW LVDS Output Mode VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 93 68 46.5 mA Sine Input, 3.5mA Mode l 95 106 70 77 48.5 54 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 39 38 38 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 74 83 74 83 74 83 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 237 191 152 mW Sine Input, 3.5mA Mode l 304 341 259 288 221 247 mW All Output Modes PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 10 10 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No increase for Nap or Sleep Modes) TIMING CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 5)LTC2182LTC2181LTC2180SYMBOL PARAMETERCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS fS Sampling Frequency (Note 10) l 1 65 1 40 1 25 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time SYMBOL PARAMETERCONDITIONSMINTYPMAXUNITSDigital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 218210f 7 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS TIMING DIAGRAMS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS