Datasheet LTC2224 (Analog Devices) - 9

LTC2224
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
OE (Pin 19):
Output Enable Pin. Refer to SHDN pin
A
function.
IN– (Pin 2):
Negative Differential Analog Input.
REFHA (Pins 3, 4):
ADC High Reference. Bypass to Pins
CLOCKOUT (Pin 20):
Data Valid Output. Latch data on the 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with falling edge of CLOCKOUT. a 2.2µF ceramic capacitor and to ground with a 1µF
D0 – D11 (Pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36, 39,
ceramic capacitor.
40):
Digital Outputs. D11 is the MSB.
REFLB (Pins 5, 6):
ADC Low Reference. Bypass to Pins 3,
OGND (Pins 22, 27, 32, 38):
Output Driver Ground. 4 with 0.1µF ceramic chip capacitor. Do not connect to
OV
Pins 9, 10.
DD (Pins 23, 28, 33, 37):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip
REFHB (Pins 7, 8):
ADC High Reference. Bypass to Pins capacitors. 9, 10 with 0.1µF ceramic chip capacitor. Do not connect to
OF (Pin 41):
Over/Under Flow Output. High when an over Pins 3, 4. or under flow has occurred.
REFLA (Pins 9, 10):
ADC Low Reference. Bypass to Pins
MODE (Pin 42):
Output Format and Clock Duty Cycle 7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a Stabilizer Selection Pin. Connecting MODE to 0V selects 2.2µF ceramic capacitor and to ground with a 1µF ceramic offset binary output format and turns the clock duty cycle capacitor. stabilizer off. Connecting MODE to 1/3 VDD selects offset
VDD (Pins 11, 12, 14, 46, 47):
3.3V Supply. Bypass to binary output format and turns the clock duty cycle stabi- GND with 0.1µF ceramic chip capacitors. Adjacent pins lizer on. Connecting MODE to 2/3 VDD selects 2’s comple- can share a bypass capacitor. ment output format and turns the clock duty cycle stabi-
GND (Pins 13, 15, 45, 48):
ADC Power Ground. lizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
ENC+ (Pin 16):
Encode Input. The input is sampled on the positive edge.
SENSE (Pin 43):
Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V
ENC– (Pin 17):
Encode Complement Input. The input is input range. VDD selects the internal reference and a ±1V sampled on the negative edge. Bypass to ground with input range. An external reference greater than 0.5V and 0.1µF ceramic for single-ended ENCODE signal. less than 1V applied to SENSE selects an input range of
SHDN (Pin 18):
Shutdown Mode Selection Pin. Connect- ±VSENSE. ±1V is the largest valid input range. ing SHDN to GND and OE to GND results in normal
VCM (Pin 44):
1.6V Output and Input Common Mode Bias. operation with the outputs enabled. Connecting SHDN to Bypass to ground with 2.2µF ceramic chip capacitor. GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to V
Exposed Pad (Pin 49):
ADC Power Ground. The exposed DD and OE to GND results in nap mode with the outputs at high pad on the bottom of the package needs to be soldered to impedance. Connecting SHDN to V ground. DD and OE to VDD results in sleep mode with the outputs at high impedance. 2224fa 9