Datasheet LTC1799 (Analog Devices) - 6

LTC1799
Theory oF operaTion
As shown in the Block Diagram, the LTC1799’s master (Pin 5). The divide-by value is determined by the state of oscillator is controlled by the ratio of the voltage between the DIV input (Pin 4). Tie DIV to GND or drive it below 0.5V the V+ and SET pins and the current entering the SET pin to select ÷1. This is the highest frequency range, with the (IRES). The voltage on the SET pin is forced to approximately master output frequency passed directly to OUT. The DIV 1.13V below V+ by the PMOS transistor and its gate bias pin may be floated or driven to midsupply to select ÷10, voltage. This voltage is accurate to ±7% at a particular the intermediate frequency range. The lowest frequency input current and supply voltage (see Figure 1). The ef- range, ÷100, is selected by tying DIV to V+ or driving it to fective input resistance is approximately 2k. within 0.4V of V+. Figure 2 shows the relationship between A resistor R RSET, divider setting and output frequency, including the SET, connected between the V+ and SET pins, “locks together” the voltage (V+ – V overlapping frequency ranges near 100kHz and 1MHz. SET) and current, IRES, variation. This provides the LTC1799’s high precision. The The CMOS output driver has an on resistance that is typi- master oscillation frequency reduces to: cally less than 100Ω. In the ÷1 (high frequency) mode, the rise and fall times are typically 7ns with a 5V supply ⎛ ⎞ ƒ and 11ns with a 3V supply. These times maintain a clean MO = 10MHz • 10kΩ ⎜ ⎟ ⎝ R SET ⎠ square wave at 10MHz (20MHz at 5V supply). In the ÷10 and ÷100 modes, where the output frequency is much lower, The LTC1799 is optimized for use with resistors between slew rate control circuitry in the output driver increases 10k and 200k, corresponding to master oscillator frequen- the rise/fall times to typically 14ns for a 5V supply and cies between 0.5MHz and 10MHz. Accurate frequencies up 19ns for a 3V supply. The reduced slew rate lowers EMI to 20MHz (RSET = 5k) are attainable if the supply voltage (electromagnetic interference) and supply bounce. is greater than 4V. To extend the output frequency range, the master oscillator signal may be divided by 1, 10 or 100 before driving OUT 1.4 1000 TA = 25°C 1.3 V+ = 5V ÷100 ÷10 ÷1 MOST 1.2 100 SET ACCURATE V+ = 3V OPERATION + – V 1.1 (kΩ) = V R SET V RES 1.0 10 0.9 0.8 1 1 10 100 1000 1k 10k 100k 1M 10M 100M IRES (µA) DESIRED OUTPUT FREQUENCY (Hz) 1799 F01 1799 F02
Figure 1. V+ – VSET Variation with IRES Figure 2. RSET vs Desired Output Frequency
1799fd 6 For more information www.linear.com/LTC1799 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Theory of Operation Applications Information Typical Application Package Description Revision History Typical Applications