Datasheet LTC2271 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 20Msps Serial Low Noise Dual ADC |
| 页数 / 页 | 24 / 5 — DIGITAL INPUTS AND OUTPUTS. The. denotes the specifi cations which apply … |
| 文件格式/大小 | PDF / 410 Kb |
| 文件语言 | 英语 |
DIGITAL INPUTS AND OUTPUTS. The. denotes the specifi cations which apply over the full operating
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LTC2271
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD =1.8V l 1.2 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance See Figure 11 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 μA CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance (Note 8) 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.375 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 93.3 103 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode l 9.4 10.7 mA 1-Lane Mode, 3.5mA Mode l 17.5 19.6 mA 2-Lane Mode, 1.75mA Mode l 13.4 15.5 mA 2-Lane Mode, 3.5mA Mode l 25.5 29 mA 4-Lane Mode, 1.75mA Mode l 21.9 25 mA 4-Lane Mode, 3.5mA Mode l 42 47 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode l 185 205 mW 1-Lane Mode, 3.5mA Mode l 199 221 mW 2-Lane Mode, 1.75mA Mode l 192 214 mW 2-Lane Mode, 3.5mA Mode l 214 238 mW 4-Lane Mode, 1.75mA Mode l 207 231 mW 4-Lane Mode, 3.5mA Mode l 244 270 mW PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 50 mW PDIFFCLK Power Increase with Diffential Encode Mode Enabled 20 mW (No Increase for Sleep Mode) 2271f 5
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD =1.8V l 1.2 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance See Figure 11 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 μA CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance (Note 8) 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.375 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 93.3 103 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode l 9.4 10.7 mA 1-Lane Mode, 3.5mA Mode l 17.5 19.6 mA 2-Lane Mode, 1.75mA Mode l 13.4 15.5 mA 2-Lane Mode, 3.5mA Mode l 25.5 29 mA 4-Lane Mode, 1.75mA Mode l 21.9 25 mA 4-Lane Mode, 3.5mA Mode l 42 47 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode l 185 205 mW 1-Lane Mode, 3.5mA Mode l 199 221 mW 2-Lane Mode, 1.75mA Mode l 192 214 mW 2-Lane Mode, 3.5mA Mode l 214 238 mW 4-Lane Mode, 1.75mA Mode l 207 231 mW 4-Lane Mode, 3.5mA Mode l 244 270 mW PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 50 mW PDIFFCLK Power Increase with Diffential Encode Mode Enabled 20 mW (No Increase for Sleep Mode) 2271f 5