Datasheet LTC2285 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Dual 14-Bit, 125Msps Low Power 3V ADC |
| 页数 / 页 | 24 / 10 — TIMING DIAGRAMS. Dual Digital Output Bus Timing. (Only One Channel is … |
| 文件格式/大小 | PDF / 594 Kb |
| 文件语言 | 英语 |
TIMING DIAGRAMS. Dual Digital Output Bus Timing. (Only One Channel is Shown). Multiplexed Digital Output Bus Timing
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LTC2285
TIMING DIAGRAMS Dual Digital Output Bus Timing (Only One Channel is Shown)
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLKA = CLKB tD D0-D13, OF N – 5 N – 4 N – 3 N – 2 N – 1 N 2284 TD01 tC CLKOUT
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX D0A-D13A A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD D0B-D13B B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 2284 TD02 tC CLKOUT 2285fb 10
TIMING DIAGRAMS Dual Digital Output Bus Timing (Only One Channel is Shown)
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLKA = CLKB tD D0-D13, OF N – 5 N – 4 N – 3 N – 2 N – 1 N 2284 TD01 tC CLKOUT
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX D0A-D13A A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD D0B-D13B B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 2284 TD02 tC CLKOUT 2285fb 10