Datasheet LTC2312-14 (Analog Devices) - 10

LTC2312-14
APPLICATIONS INFORMATION Overview Serial Data Output (SDO)
The LTC2312-14 is a low noise, high speed, 14-bit succes- The SDO output is always forced into the high imped- sive approximation register (SAR) ADC. The LTC2312-14 ance state while CONV is high. The falling edge of CONV operates from a single 3V or 5V supply and provides a low enables SDO and also places the sample and hold into drift (20ppm/°C maximum), internal reference and refer- sample mode. The A/D conversion result is shifted out ence buffer. The internal reference buffer is automatically on the SDO pin as a serial data stream with the MSB first. configured with a 2.048V span in low supply range (2.7V The MSB is output on SDO on the falling edge of CONV. to 3.6V) and with a 4.096V span in the high supply range Delay t3 is the data valid access time for the MSB. The (4.75V to 5.25V). The LTC2312-14 samples at a 500ksps following 13 bits of conversion data are shifted out on rate and supports a 20MHz serial data read clock. The SDO on the falling edge of SCK. Delay t4 is the data valid LTC2312-14 achieves excellent dynamic performance access time for output data shifted out on the falling edge (77dB SINAD, 85dB THD) while dissipating only 15mW of SCK. There is no data latency. Subsequent falling SCK from a 5V supply up to the 500ksps conversion rate. The edges applied after the LSB is output will output zeros LTC2312-14 outputs the conversion data with no cycle indefinitely on the SDO pin. latency onto the SDO pin. The SDO pin output logic lev- The output swing on the SDO pin is controlled by the els are supplied by the dedicated OVDD supply pin which OV has a wide supply range (1.71V to 5.25V) allowing the DD pin voltage and supports a wide operating range from 1.71V to 5.25V independent of the V LTC2312-14 to communicate with 1.8V, 2.5V, 3V or 5V DD pin voltage. systems. The LTC2312-14 automatically switches to nap
Power Considerations
mode following the conversion process to save power. The device also provides a sleep power-down mode through The LTC2312-14 provides two sets of power supply pins: serial interface control to reduce power dissipation during the analog power supply (VDD) and the digital input/output long inactive periods. interface power supply (OVDD). The flexible OVDD supply allows the LTC2312-14 to communicate with any digital
Serial Interface
logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The LTC2312-14 communicates with microcontrollers, DSPs and other external circuitry via a 3-wire interface.
Entering Nap/Sleep Mode
A rising CONV edge starts the conversion process which is timed via an internal oscillator. Following the conver- Pulsing CONV two times and holding SCK static places the sion process the device automatically switches to nap LTC2312-14 into nap mode. Pulsing CONV four times and mode to save power as shown in Figure 7. This feature holding SCK static places the LTC2312-14 into sleep mode. saves considerable power for the LTC2312-14 operating In sleep mode, all bias circuitry is shut down, including the at lower sampling rates. As shown in Figures 5 and 6, it internal bandgap and reference buffer, and only leakage is recommended to hold SCK static low or high during currents remain (0.2µA typical). Because the reference t buffer is externally bypassed with a large capacitor (2.2µF), CONV. Note that CONV must be held high for the entire minimum conversion time (t the LTC2312-14 requires a significant wait time (1.1ms) to CONV). A falling CONV edge enables SDO and outputs the MSB. Subsequent SCK recharge this capacitance before an accurate conversion falling edges clock out the remaining data as shown in can be made. In contrast, nap mode does not power down Figures 5 and 6. Data is serially output MSB first through the internal bandgap or reference buffer allowing for a fast LSB last, followed by trailing zeros if further SCK falling wake-up and accurate conversion within one conversion clock edges are applied. cycle. Supply current during nap mode is nominally 2mA. 231214fa 10 For more information www.linear.com/LTC2312-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts