Datasheet LTC2320-16 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Octal, 16-Bit, 1.5Msps/Ch Simultaneous Sampling ADC |
| 页数 / 页 | 32 / 6 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
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LTC2320-16
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1.5 Msps tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l 0.667 1000 µs tCONV Conversion Time l 450 ns tCNVH CNV High Time l 30 ns tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 215 ns tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms
CMOS I/O Mode, SDR
CMOS/LVDS = GND, SDR/ DDR = GND tSCK SCK Period (Note 13) l 9.1 ns tSCKH SCK High Time l 4.1 ns tSCKL SCK Low Time l 4.1 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
CMOS I/O Mode, DDR
CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF, OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, SDR
CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF, OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, DDR
CMOS/LVDS = OVDD, SDR/DDR = OVDD tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns 232016fb 6 For more information www.linear.com/LTC2320-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts .32673 Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1.5 Msps tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l 0.667 1000 µs tCONV Conversion Time l 450 ns tCNVH CNV High Time l 30 ns tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 215 ns tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms
CMOS I/O Mode, SDR
CMOS/LVDS = GND, SDR/ DDR = GND tSCK SCK Period (Note 13) l 9.1 ns tSCKH SCK High Time l 4.1 ns tSCKL SCK Low Time l 4.1 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
CMOS I/O Mode, DDR
CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF, OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, SDR
CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF, OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, DDR
CMOS/LVDS = OVDD, SDR/DDR = OVDD tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns 232016fb 6 For more information www.linear.com/LTC2320-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts .32673 Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts