Datasheet LTC2360, LTC2361, LTC2362 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 500ksps, 12-Bit Serial ADCs in TSOT-23 |
| 页数 / 页 | 20 / 9 — PIN FUNCTIONS. S6 Package. TS8 Package. VDD (Pin 1):. VREF (Pin 2):. GND … |
| 文件格式/大小 | PDF / 325 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. S6 Package. TS8 Package. VDD (Pin 1):. VREF (Pin 2):. GND (Pin 2):. AIN (Pin 3):. GND (Pin 3):. SCK (Pin 4):. AIN (Pin 4):
该数据表的模型线
- LTC2360CS6#PBF LTC2360CS6#TRMPBF LTC2360CS6#TRMPBF LTC2360CS6#TRPBF LTC2360CS6#TRPBF LTC2360CTS8#PBF LTC2360CTS8#TRMPBF LTC2360CTS8#TRMPBF LTC2360CTS8#TRPBF LTC2360CTS8#TRPBF LTC2360HS6#PBF LTC2360HS6#TRMPBF LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTC2360HS6#TRPBF LTC2360HTS8#PBF LTC2360HTS8#TRMPBF LTC2360HTS8#TRMPBF LTC2360HTS8#TRPBF LTC2360HTS8#TRPBF LTC2360IS6#PBF LTC2360IS6#TRMPBF LTC2360IS6#TRMPBF LTC2360IS6#TRPBF LTC2360IS6#TRPBF LTC2360ITS8#PBF LTC2360ITS8#TRMPBF LTC2360ITS8#TRMPBF LTC2360ITS8#TRPBF LTC2360ITS8#TRPBF
- LTC2361CS6#PBF LTC2361CS6#TRMPBF LTC2361CS6#TRMPBF LTC2361CS6#TRPBF LTC2361CS6#TRPBF LTC2361CTS8#PBF LTC2361CTS8#TRMPBF LTC2361CTS8#TRMPBF LTC2361CTS8#TRPBF LTC2361CTS8#TRPBF LTC2361HS6#PBF LTC2361HS6#TRMPBF LTC2361HS6#TRMPBF LTC2361HS6#TRPBF LTC2361HS6#TRPBF LTC2361HTS8#PBF LTC2361HTS8#TRMPBF LTC2361HTS8#TRMPBF LTC2361HTS8#TRPBF LTC2361HTS8#TRPBF LTC2361IS6#PBF LTC2361IS6#TRMPBF LTC2361IS6#TRMPBF LTC2361IS6#TRPBF LTC2361IS6#TRPBF LTC2361ITS8#PBF LTC2361ITS8#TRMPBF LTC2361ITS8#TRMPBF LTC2361ITS8#TRPBF LTC2361ITS8#TRPBF
- LTC2362CS6#PBF LTC2362CS6#TRMPBF LTC2362CS6#TRMPBF LTC2362CS6#TRPBF LTC2362CS6#TRPBF LTC2362CTS8#PBF LTC2362CTS8#TRMPBF LTC2362CTS8#TRMPBF LTC2362CTS8#TRPBF LTC2362CTS8#TRPBF LTC2362HS6#PBF LTC2362HS6#TRMPBF LTC2362HS6#TRMPBF LTC2362HS6#TRPBF LTC2362HS6#TRPBF LTC2362HTS8#PBF LTC2362HTS8#TRMPBF LTC2362HTS8#TRMPBF LTC2362HTS8#TRPBF LTC2362HTS8#TRPBF LTC2362IS6#PBF LTC2362IS6#TRMPBF LTC2362IS6#TRMPBF LTC2362IS6#TRPBF LTC2362IS6#TRPBF LTC2362ITS8#PBF LTC2362ITS8#TRMPBF LTC2362ITS8#TRMPBF LTC2362ITS8#TRPBF LTC2362ITS8#TRPBF
文件文字版本
LTC2360/LTC2361/LTC2362
PIN FUNCTIONS S6 Package TS8 Package VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to
VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defi nes the input span of the ADC, 0V to 3.6V. Bypass to GND and to a solid ground plane with a VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). with 0.1μF ceramic).
VREF (Pin 2):
Reference Input. VREF defi nes the input
GND (Pin 2):
Ground. The GND pin must be tied directly span of the ADC, 0V to VREF. The VREF range is 1.4V to to a solid ground plane. VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel
AIN (Pin 3):
Analog Input. AIN is a single-ended input with with 0.1μF ceramic). respect to GND with a range from 0V to VDD.
GND (Pin 3):
Ground. The GND pin must be tied directly
SCK (Pin 4):
Shift Clock Input. The SCK serial clock syn- to a solid ground plane. chronizes the serial data transfer. SDO data transitions on the falling edge of SCK.
AIN (Pin 4):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V
SDO (Pin 5):
Three-State Serial Data Output. The A/D REF. conversion result is shifted out on SDO as a serial data
OVDD (Pin 5):
Output Driver Supply for SDO. The OVDD stream with MSB fi rst. The data stream consists of 12 bits range is 1V to VDD. Bypass to GND and to a solid ground of conversion data followed by trailing zeros. plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). OV
CONV (Pin 6):
Convert Input. This active high signal starts DD can be driven separately from V a conversion on the rising edge. The device automatically DD and OVDD can be higher than VDD. powers down after conversion. A logic low on this input
SDO (Pin 6):
Three-State Serial Data Output. The A/D enables the SDO pin, allowing the data to be shifted out. conversion result is shifted out on SDO as a serial data stream with MSB fi rst. The data stream consists of 12 bits of conversion data followed by trailing zeros.
SCK (Pin 7):
Shift Clock Input. The SCK serial clock syn- chronizes the serial data transfer. SDO data transitions on the falling edge of SCK.
CONV (Pin 8):
Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. 236012fa 9
PIN FUNCTIONS S6 Package TS8 Package VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to
VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defi nes the input span of the ADC, 0V to 3.6V. Bypass to GND and to a solid ground plane with a VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). with 0.1μF ceramic).
VREF (Pin 2):
Reference Input. VREF defi nes the input
GND (Pin 2):
Ground. The GND pin must be tied directly span of the ADC, 0V to VREF. The VREF range is 1.4V to to a solid ground plane. VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel
AIN (Pin 3):
Analog Input. AIN is a single-ended input with with 0.1μF ceramic). respect to GND with a range from 0V to VDD.
GND (Pin 3):
Ground. The GND pin must be tied directly
SCK (Pin 4):
Shift Clock Input. The SCK serial clock syn- to a solid ground plane. chronizes the serial data transfer. SDO data transitions on the falling edge of SCK.
AIN (Pin 4):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V
SDO (Pin 5):
Three-State Serial Data Output. The A/D REF. conversion result is shifted out on SDO as a serial data
OVDD (Pin 5):
Output Driver Supply for SDO. The OVDD stream with MSB fi rst. The data stream consists of 12 bits range is 1V to VDD. Bypass to GND and to a solid ground of conversion data followed by trailing zeros. plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). OV
CONV (Pin 6):
Convert Input. This active high signal starts DD can be driven separately from V a conversion on the rising edge. The device automatically DD and OVDD can be higher than VDD. powers down after conversion. A logic low on this input
SDO (Pin 6):
Three-State Serial Data Output. The A/D enables the SDO pin, allowing the data to be shifted out. conversion result is shifted out on SDO as a serial data stream with MSB fi rst. The data stream consists of 12 bits of conversion data followed by trailing zeros.
SCK (Pin 7):
Shift Clock Input. The SCK serial clock syn- chronizes the serial data transfer. SDO data transitions on the falling edge of SCK.
CONV (Pin 8):
Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. 236012fa 9