Datasheet LTC2360, LTC2361, LTC2362 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 500ksps, 12-Bit Serial ADCs in TSOT-23 |
| 页数 / 页 | 20 / 10 — BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Into Hi-Z State After CONV … |
| 文件格式/大小 | PDF / 325 Kb |
| 文件语言 | 英语 |
BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Into Hi-Z State After CONV Rising Edge
该数据表的模型线
- LTC2360CS6#PBF LTC2360CS6#TRMPBF LTC2360CS6#TRMPBF LTC2360CS6#TRPBF LTC2360CS6#TRPBF LTC2360CTS8#PBF LTC2360CTS8#TRMPBF LTC2360CTS8#TRMPBF LTC2360CTS8#TRPBF LTC2360CTS8#TRPBF LTC2360HS6#PBF LTC2360HS6#TRMPBF LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTC2360HS6#TRPBF LTC2360HTS8#PBF LTC2360HTS8#TRMPBF LTC2360HTS8#TRMPBF LTC2360HTS8#TRPBF LTC2360HTS8#TRPBF LTC2360IS6#PBF LTC2360IS6#TRMPBF LTC2360IS6#TRMPBF LTC2360IS6#TRPBF LTC2360IS6#TRPBF LTC2360ITS8#PBF LTC2360ITS8#TRMPBF LTC2360ITS8#TRMPBF LTC2360ITS8#TRPBF LTC2360ITS8#TRPBF
- LTC2361CS6#PBF LTC2361CS6#TRMPBF LTC2361CS6#TRMPBF LTC2361CS6#TRPBF LTC2361CS6#TRPBF LTC2361CTS8#PBF LTC2361CTS8#TRMPBF LTC2361CTS8#TRMPBF LTC2361CTS8#TRPBF LTC2361CTS8#TRPBF LTC2361HS6#PBF LTC2361HS6#TRMPBF LTC2361HS6#TRMPBF LTC2361HS6#TRPBF LTC2361HS6#TRPBF LTC2361HTS8#PBF LTC2361HTS8#TRMPBF LTC2361HTS8#TRMPBF LTC2361HTS8#TRPBF LTC2361HTS8#TRPBF LTC2361IS6#PBF LTC2361IS6#TRMPBF LTC2361IS6#TRMPBF LTC2361IS6#TRPBF LTC2361IS6#TRPBF LTC2361ITS8#PBF LTC2361ITS8#TRMPBF LTC2361ITS8#TRMPBF LTC2361ITS8#TRPBF LTC2361ITS8#TRPBF
- LTC2362CS6#PBF LTC2362CS6#TRMPBF LTC2362CS6#TRMPBF LTC2362CS6#TRPBF LTC2362CS6#TRPBF LTC2362CTS8#PBF LTC2362CTS8#TRMPBF LTC2362CTS8#TRMPBF LTC2362CTS8#TRPBF LTC2362CTS8#TRPBF LTC2362HS6#PBF LTC2362HS6#TRMPBF LTC2362HS6#TRMPBF LTC2362HS6#TRPBF LTC2362HS6#TRPBF LTC2362HTS8#PBF LTC2362HTS8#TRMPBF LTC2362HTS8#TRMPBF LTC2362HTS8#TRPBF LTC2362HTS8#TRPBF LTC2362IS6#PBF LTC2362IS6#TRMPBF LTC2362IS6#TRMPBF LTC2362IS6#TRPBF LTC2362IS6#TRPBF LTC2362ITS8#PBF LTC2362ITS8#TRMPBF LTC2362ITS8#TRMPBF LTC2362ITS8#TRPBF LTC2362ITS8#TRPBF
文件文字版本
LTC2360/LTC2361/LTC2362
BLOCK DIAGRAM
2.2μF 2.2μF + + 1 5 VDD OVDD ANALOG AIN INPUT 4 RANGE THREE-STATE SDO 0V TO V SERIAL REF S AND H 12-BIT ADC 6 OUTPUT PORT VREF 2 SCK 7 2.2μF GND TIMING LOGIC CONV 3 8 TS8 PACKAGE 236012 BD
TIMING DIAGRAMS
t8 t7 CONV 1.6V SCK 1.6V Hi-Z SDO VIH 236012 F01 SDO VIL 236012 F02
Figure 1. SDO Into Hi-Z State After CONV Rising Edge Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t4 SCK 1.6V VIH SDO VIL 236012 F03
Figure 3. SDO Data Valid Acess Time After SCK Falling Edge
236012fa 10
BLOCK DIAGRAM
2.2μF 2.2μF + + 1 5 VDD OVDD ANALOG AIN INPUT 4 RANGE THREE-STATE SDO 0V TO V SERIAL REF S AND H 12-BIT ADC 6 OUTPUT PORT VREF 2 SCK 7 2.2μF GND TIMING LOGIC CONV 3 8 TS8 PACKAGE 236012 BD
TIMING DIAGRAMS
t8 t7 CONV 1.6V SCK 1.6V Hi-Z SDO VIH 236012 F01 SDO VIL 236012 F02
Figure 1. SDO Into Hi-Z State After CONV Rising Edge Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t4 SCK 1.6V VIH SDO VIL 236012 F03
Figure 3. SDO Data Valid Acess Time After SCK Falling Edge
236012fa 10