Datasheet LTC2451 (Analog Devices) - 8

LTC2451
APPLICATIONS INFORMATION CONVERTER OPERATION
SCL, allowing the user to reliably latch data on the rising edge of SCL. In write operation, the device accepts one
Converter Operation Cycle
configuration byte and the data is shifted in on the rising The LTC2451 is a low power, delta-sigma analog-to- edges of SCL. A new conversion is initiated by a STOP digital converter with an I2C interface. Its operation, as condition following a valid read or write operation, or by shown in Figure 1, is composed of three successive states: the conclusion of a complete read cycle (all 16 bits read conversion, sleep, and data input/output. out of the device). Initially, at power-up, the LTC2451 is set to its default 60Hz
Power-Up Sequence
mode and performs a conversion. Once the conversion is When the power supply voltage, VCC, applied to the con- complete, the device enters the sleep state. While in the verter is below approximately 2.1V, the ADC performs a sleep state, power consumption is reduced by several power-on reset. This feature guarantees the integrity of orders of magnitude. The part remains in the sleep state the conversion result. as long it is not addressed for a read or write operation. The conversion result is held indefinitely in a static shift When VCC rises above this threshold, the converter register while the part is in the sleep state. generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal The device will not acknowledge an external request dur- registers. Following the POR signal, the LTC2451 starts ing the conversion state. After a conversion is finished, a conversion cycle and follows the succession of states the device is ready to accept a read/write request. The described in Figure 1. The first conversion result follow- LTC2451’s address is hard wired at 0010100. Once the ing POR is accurate within the specifications of the device LTC2451 is addressed for a read operation, the device if the power supply voltage, VCC, is restored within the begins outputting the conversion result under the control operating range (2.7V to 5.5V) before the end of the POR of the serial clock (SCL). There is no latency in the conver- time interval. sion result. The data output is 16 bits long and outputs from MSB to LSB. Data is updated on the falling edges of
Ease of Use
The LTC2451 data output has no latency, filter settling POWER-ON RESET delay, or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the CONVERSION conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. SLEEP In the 30Hz mode, the LTC2451 performs offset calibrations during every conversion. This calibration is transparent to NO READ/WRITE ACKNOWLEDGE the user and has no effect upon the cyclic operation previ- ously described. The advantage of continuous calibration YES is stability of the ADC performance with respect to time DATA INPUT/OUTPUT and temperature. The LTC2451 includes a proprietary input sampling scheme STOP that reduces the average input current by several orders NO OR READ of magnitude when compared to traditional delta-sigma 16 BITS architectures. This allows external filter networks to interface YES directly to the LTC2451. Since the average input sampling 2451 F01 current is 50nA, an external RC lowpass filter using a 1kΩ
Figure 1. State Diagram
and 0.1µF results in less than 1LSB additional error. 2451fg 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Input And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts