Datasheet LTC2451 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Ultra-Tiny, 16-Bit ΔΣ ADC with I2C Interface |
| 页数 / 页 | 20 / 10 — APPLICATIONS INFORMATION. Data Transferring. Data Format. Figure 3. … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
APPLICATIONS INFORMATION. Data Transferring. Data Format. Figure 3. Timing Diagram for Write Sequence
该数据表的模型线
- LTC2451CDDB#PBF LTC2451CDDB#TRMPBF LTC2451CDDB#TRMPBF LTC2451CDDB#TRPBF LTC2451CDDB#TRPBF LTC2451CTS8#PBF LTC2451CTS8#TRMPBF LTC2451CTS8#TRMPBF LTC2451CTS8#TRPBF LTC2451CTS8#TRPBF LTC2451IDDB#PBF LTC2451IDDB#TRMPBF LTC2451IDDB#TRMPBF LTC2451IDDB#TRPBF LTC2451IDDB#TRPBF LTC2451ITS8#PBF LTC2451ITS8#TRMPBF LTC2451ITS8#TRMPBF LTC2451ITS8#TRPBF LTC2451ITS8#TRPBF
文件文字版本
LTC2451
APPLICATIONS INFORMATION Data Transferring
and 0 for a write request. If the 7-bit address agrees with After the START condition, the I2C bus is busy and data the LTC2451’s address, the device is selected. When the transfer can begin between the master and the addressed device is addressed during the conversion state, it does slave. Data is transferred over the bus in groups of nine not accept the request and issues a NACK by leaving the bits, one byte followed by one acknowledge (ACK) bit. The SDA line high. If the conversion is complete, the LTC2451 master releases the SDA line during the ninth SCL clock issues an ACK by pulling the SDA line LOW. cycle. The slave device can issue an ACK by pulling SDA The user can send one byte of data into the LTC2451 fol- LOW or issue a not-acknowledge (NACK) by leaving the lowing a write request and an ACK. The sequence is shown SDA line high impedance (the external pull-up resistor will in Figure 3. The write sequence is used solely to set the hold the line high). Change of data only occurs while the conversion speed. The default conversion speed is 60Hz. clock line (SCL) is low. The user can specify a 30Hz conversion speed by setting the eighth bit (S30) = 1, or specify a 60Hz conversion
Data Format
speed by setting the eighth bit (S30) = 0. After a START condition, the master sends a 7-bit address After a read request and an ACK, the LTC2451 can output (factory set at 0010100), followed by a read request (R) data, as shown in Figure 4. The data output stream is 16 or write request (W) bit. The bit R is 1 for a read request bits long and is shifted out on the falling edges of SCL. 1 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA 7-BIT W S30 = 1: 30Hz MODE S30 ADDRESS S30 = 0: 60Hz MODE START BY ACK BY ACK BY MASTER LTC2451 MASTER SLEEP DATA INPUT 2451 F03
Figure 3. Timing Diagram for Write Sequence
1 7 8 9 1 2 3 8 9 1 2 3 8 9 SCL 7-BIT SDA R D15 D14 D13 D8 ADDRESS D7 D6 D5 D0 MSB LSB START BY ACK BY ACK BY NACK BY MASTER LTC2451 MASTER MASTER SLEEP DATA OUTPUT CONVERT 2451 F04
Figure 4. Timing Diagram for Read Sequence
2451fg 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Input And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION Data Transferring
and 0 for a write request. If the 7-bit address agrees with After the START condition, the I2C bus is busy and data the LTC2451’s address, the device is selected. When the transfer can begin between the master and the addressed device is addressed during the conversion state, it does slave. Data is transferred over the bus in groups of nine not accept the request and issues a NACK by leaving the bits, one byte followed by one acknowledge (ACK) bit. The SDA line high. If the conversion is complete, the LTC2451 master releases the SDA line during the ninth SCL clock issues an ACK by pulling the SDA line LOW. cycle. The slave device can issue an ACK by pulling SDA The user can send one byte of data into the LTC2451 fol- LOW or issue a not-acknowledge (NACK) by leaving the lowing a write request and an ACK. The sequence is shown SDA line high impedance (the external pull-up resistor will in Figure 3. The write sequence is used solely to set the hold the line high). Change of data only occurs while the conversion speed. The default conversion speed is 60Hz. clock line (SCL) is low. The user can specify a 30Hz conversion speed by setting the eighth bit (S30) = 1, or specify a 60Hz conversion
Data Format
speed by setting the eighth bit (S30) = 0. After a START condition, the master sends a 7-bit address After a read request and an ACK, the LTC2451 can output (factory set at 0010100), followed by a read request (R) data, as shown in Figure 4. The data output stream is 16 or write request (W) bit. The bit R is 1 for a read request bits long and is shifted out on the falling edges of SCL. 1 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA 7-BIT W S30 = 1: 30Hz MODE S30 ADDRESS S30 = 0: 60Hz MODE START BY ACK BY ACK BY MASTER LTC2451 MASTER SLEEP DATA INPUT 2451 F03
Figure 3. Timing Diagram for Write Sequence
1 7 8 9 1 2 3 8 9 1 2 3 8 9 SCL 7-BIT SDA R D15 D14 D13 D8 ADDRESS D7 D6 D5 D0 MSB LSB START BY ACK BY ACK BY NACK BY MASTER LTC2451 MASTER MASTER SLEEP DATA OUTPUT CONVERT 2451 F04
Figure 4. Timing Diagram for Read Sequence
2451fg 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Input And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts