Datasheet LTC2460, LTC2462 (Analog Devices) - 9

LTC2460/LTC2462
applicaTions inForMaTion
between the conversion and the output data. Therefore,
Input Voltage Range (LTC2462)
multiplexing multiple analog input voltages requires no As mentioned in the Output Data Format section, the output special actions. code is given as 32768 • (V + – IN – VIN )/VREF + 32768. For The LTC2460/LTC2462 perform offset calibrations every (V + – IN – VIN ) ≥ VREF, the output code is clamped at 65535 conversion. This calibration is transparent to the user and (all ones). For (V + – IN – VIN ) ≤ –VREF, the output code is has no effect upon the cyclic operation described previously. clamped at 0 (all zeroes). The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2462 includes a proprietary architecture that can, typically, digitize each input up to 8 LSBs above VREF The LTC2460/LTC2462 include a proprietary input sampling and below GND, if the differential input is within ±VREF. scheme that reduces the average input current by several As an example (Figure 3), if the user desires to measure orders of magnitude when compared to traditional delta- a signal slightly below ground, the user could set V – IN sigma architectures. This allows external filter networks = GND, and V + REF = 1.25V. If VIN = GND, the output code to interface directly to the LTC2460/LTC2462. Since the would be approximately 32768. If V + IN = GND – 8LSB = average input sampling current is 50nA, an external RC –0.305mV, the output code would be approximately 32760. lowpass filter using 1kΩ and 0.1µF results in <1LSB For applications that require an input range greater than additional error. Additionally, there is negligible leakage ±1.25V, please refer to the LTC2452. current between IN+ and IN–.
Output Data Format Input Voltage Range (LTC2460)
The LTC2460/LTC2462 generates a 16-bit direct binary Ignoring offset and full-scale errors, the LTC2460 will encoded result. It is provided as a 16-bit serial stream theoretically output an “all zero” digital result when the through the SDO output pin under the control of the SCK input is at ground (a zero scale input) and an “all one” input pin (see Figure 4). digital result when the input is at VREF (VREFOUT = 1.25V). The LTC2462 (differential input) output code is given by In an under-range condition, for all input voltages below 32768 • (V + – IN – VIN )/VREF + 32768. The first bit output zero scale, the converter will generate the output code 0. In by the LTC2462, D15, is the MSB, which is 1 for V + IN ≥ an over-range condition, for all input voltages greater than V – + – IN and 0 for VIN < VIN . This bit is followed by succes- VREF, the converter will generate the output code 65535. sively less significant bits (D14, D13, …) until the LSB is For applications that require an input range greater than output by the LTC2462, see Table 1. 0V to 1.25V, please refer to the LTC2450. t3 t t 1 2 CS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO MSB LSB SCK tKQ tlSCK thSCK EN1 EN2 SPD* SLP SDI DON’T CARE 24602 F04 t5 t6 *SPD IS A DON’T CARE BIT FOR THE LTC2462
Figure 4. Data Input/Output Timing
24602fa 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts