Datasheet LTM9002 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 125Msps Dual-Channel IF/Baseband Receiver Subsystem |
| 页数 / 页 | 28 / 6 — The. TIMING CHARACTERISTICS. denotes the specifi cations which apply over … |
| 文件格式/大小 | PDF / 355 Kb |
| 文件语言 | 英语 |
The. TIMING CHARACTERISTICS. denotes the specifi cations which apply over the full operating temperature
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文件文字版本
LTM9002
The TIMING CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency LTM9002-AA l 1 125 MHz LTM9002-LA l 1 65 MHz tL CLK Low Time Duty Cycle Stabilizer Off (Note 6), LTM9002-AA l 3.8 4 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-AA l 3 4 500 ns tH CLK High Time Duty Cycle Stabilizer Off (Note 6), LTM9002-AA l 3.8 4 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-AA l 3 4 500 ns tL CLK Low Time Duty Cycle Stabilizer Off (Note 6), LTM9002-LA l 7.3 7.7 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-LA l 5 7.7 500 ns tH CLK High Time Duty Cycle Stabilizer Off (Note 6), LTM9002-LA l 7.3 7.7 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-LA l 5 7.7 500 ns tAP Absolute Aperture Delay 0 ns tD CLK to DATA Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns tC CLK to CLKOUT Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns DATA to CLKOUT Skew (tD – tC) (Note 6) l –0.6 0 0.6 ns tMD MUX to DATA Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns DATA Access Time After OE↓ CL = 5pF (Note 6) l 4.3 10 ns BUS Relinquish Time (Note 6) l 3.3 8.5 ns Pipeline Latency 5 Cycles
SPI Interface for Aux DACs, VDD = 2.7V to 3.6V
t1 SDI Valid to SCK Setup 4 ns t2 SDI Valid to SCK Hold 4 ns t3 SCK High Time 9 ns t4 SCK Low Time 9 ns t5 CS/LD Pulse Width 10 ns t6 LSB SCK High to CS/LD 7 ns t7 CS/LD Low to SCK High 7 ns t10 CS/LD High to SCK Positive Edge 7 ns SCK Frequency 50% Duty Cycle 50 MHz
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
Integral nonlinearity is defi ned as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 5:
Offset error is the output code resulting when the inputs are
Note 2:
All voltage values are with respect to ground with GND and OGND shorted together. The output code is converted to millivolts. wired together (unless otherwise noted).
Note 6:
Guaranteed by design, not subject to test.
Note 3:
OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN
Note 7:
VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive. with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN = The supply current and power dissipation are the sum total for both ADCSHDN = 0V, unless otherwise noted. channels with both channels active. 9002f 6
The TIMING CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency LTM9002-AA l 1 125 MHz LTM9002-LA l 1 65 MHz tL CLK Low Time Duty Cycle Stabilizer Off (Note 6), LTM9002-AA l 3.8 4 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-AA l 3 4 500 ns tH CLK High Time Duty Cycle Stabilizer Off (Note 6), LTM9002-AA l 3.8 4 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-AA l 3 4 500 ns tL CLK Low Time Duty Cycle Stabilizer Off (Note 6), LTM9002-LA l 7.3 7.7 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-LA l 5 7.7 500 ns tH CLK High Time Duty Cycle Stabilizer Off (Note 6), LTM9002-LA l 7.3 7.7 500 ns Duty Cycle Stabilizer On (Note 6), LTM9002-LA l 5 7.7 500 ns tAP Absolute Aperture Delay 0 ns tD CLK to DATA Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns tC CLK to CLKOUT Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns DATA to CLKOUT Skew (tD – tC) (Note 6) l –0.6 0 0.6 ns tMD MUX to DATA Delay CL = 5pF (Note 6) l 1.4 2.7 5.4 ns DATA Access Time After OE↓ CL = 5pF (Note 6) l 4.3 10 ns BUS Relinquish Time (Note 6) l 3.3 8.5 ns Pipeline Latency 5 Cycles
SPI Interface for Aux DACs, VDD = 2.7V to 3.6V
t1 SDI Valid to SCK Setup 4 ns t2 SDI Valid to SCK Hold 4 ns t3 SCK High Time 9 ns t4 SCK Low Time 9 ns t5 CS/LD Pulse Width 10 ns t6 LSB SCK High to CS/LD 7 ns t7 CS/LD Low to SCK High 7 ns t10 CS/LD High to SCK Positive Edge 7 ns SCK Frequency 50% Duty Cycle 50 MHz
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
Integral nonlinearity is defi ned as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 5:
Offset error is the output code resulting when the inputs are
Note 2:
All voltage values are with respect to ground with GND and OGND shorted together. The output code is converted to millivolts. wired together (unless otherwise noted).
Note 6:
Guaranteed by design, not subject to test.
Note 3:
OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN
Note 7:
VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive. with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN = The supply current and power dissipation are the sum total for both ADCSHDN = 0V, unless otherwise noted. channels with both channels active. 9002f 6