Datasheet LTC3026-1 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 1.5A Low Input Voltage VLDO Linear Regulator |
| 页数 / 页 | 16 / 8 — OPERATION. LDO Operation. Figure 1. Output Load Step Response. Figure 2. … |
| 文件格式/大小 | PDF / 181 Kb |
| 文件语言 | 英语 |
OPERATION. LDO Operation. Figure 1. Output Load Step Response. Figure 2. Soft-Start with Boost Disable
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LTC3026-1
OPERATION
The LTC3026-1 is a VLDO (very low dropout) linear regula- 1.5A tor which operates from input voltages as low as 1.14V. IOUT 0mA The LDO uses an internal NMOS transistor as the pass device in a source-follower configuration. The BIAS pin provides the higher supply necessary for the LDO circuitry OUT AC 20mV/DIV while the output current comes directly from the IN input for high efficiency regulation. The LTC3026-1 is the same as the LTC3026 but has the boost converter disabled. The SW pin of the LTC3026 has been replaced with a GNDS pin. Because the boost V 30261 F01 OUT = 1.5V 100μs/DIV converter is disabled, an external 5V supply must be pres- COUT = 10μF ent to drive the BIAS pin (formally BST on the LTC3026). VIN = 1.7V VBIAS = 5V
LDO Operation Figure 1. Output Load Step Response
An undervoltage lockout comparator (UVLO) senses the HI BIAS pin voltage to ensure that the bias supply for the LDO SHDN is greater than 4.2V before enabling the LDO. If BIAS is LO below 4.2V, the UVLO shuts down the LDO, and OUT is 1.5V pulled to GND through the external divider. OUT The LDO provides a high accuracy output capable of sup- plying 1.5A of output current with a typical dropout voltage 0V of only 100mV. A single ceramic capacitor as small as 10μF is all that is required for output bypassing. A low reference 1.5V PG voltage allows the LTC3026-1 output to be programmed 0V to much lower voltages than available in common LDOs TA = 25°C 100μs/DIV 30261 F02 ROUT = 1Ω (range of 0.4V to 2.6V). VIN = 1.7V VBIAS = 5V The devices also include current limit and thermal overload
Figure 2. Soft-Start with Boost Disable
protection, and will survive an output short-circuit indefi- nitely. The fast transient response of the follower output stage overcomes the traditional trade-off between dropout
Adjustable Output Voltage
voltage, quiescent current and load transient response The output voltage is set by the ratio of two external resis- inherent in most LDO regulator architectures, see Figure 1. tors as shown in Figure 3. The device servos the output The LTC3026-1 also includes a soft-start feature to prevent to maintain the ADJ pin voltage at 0.4V (referenced to excessive current flow at V ground). Thus, the current in R1 is equal to 0.4V/R1. For IN during start-up. When the LDO is enabled, the soft-start circuitry gradually increases good transient response, stability and accuracy the current the LDO reference voltage from 0V to 0.4V over a period in R1 should be at least 80μA, thus, the value of R1 should of approximately 200μs, see Figure 2. be no greater than 5k. The current in R2 is the current in R1 plus the ADJ pin bias current. Since the ADJ pin bias current is typically <10nA it can be ignored in the output voltage calculation. The output voltage can be calculated using the formula in Figure 3. Note that in shutdown the output is turned off and the divider current will be zero once COUT is discharged. 30261f 8
OPERATION
The LTC3026-1 is a VLDO (very low dropout) linear regula- 1.5A tor which operates from input voltages as low as 1.14V. IOUT 0mA The LDO uses an internal NMOS transistor as the pass device in a source-follower configuration. The BIAS pin provides the higher supply necessary for the LDO circuitry OUT AC 20mV/DIV while the output current comes directly from the IN input for high efficiency regulation. The LTC3026-1 is the same as the LTC3026 but has the boost converter disabled. The SW pin of the LTC3026 has been replaced with a GNDS pin. Because the boost V 30261 F01 OUT = 1.5V 100μs/DIV converter is disabled, an external 5V supply must be pres- COUT = 10μF ent to drive the BIAS pin (formally BST on the LTC3026). VIN = 1.7V VBIAS = 5V
LDO Operation Figure 1. Output Load Step Response
An undervoltage lockout comparator (UVLO) senses the HI BIAS pin voltage to ensure that the bias supply for the LDO SHDN is greater than 4.2V before enabling the LDO. If BIAS is LO below 4.2V, the UVLO shuts down the LDO, and OUT is 1.5V pulled to GND through the external divider. OUT The LDO provides a high accuracy output capable of sup- plying 1.5A of output current with a typical dropout voltage 0V of only 100mV. A single ceramic capacitor as small as 10μF is all that is required for output bypassing. A low reference 1.5V PG voltage allows the LTC3026-1 output to be programmed 0V to much lower voltages than available in common LDOs TA = 25°C 100μs/DIV 30261 F02 ROUT = 1Ω (range of 0.4V to 2.6V). VIN = 1.7V VBIAS = 5V The devices also include current limit and thermal overload
Figure 2. Soft-Start with Boost Disable
protection, and will survive an output short-circuit indefi- nitely. The fast transient response of the follower output stage overcomes the traditional trade-off between dropout
Adjustable Output Voltage
voltage, quiescent current and load transient response The output voltage is set by the ratio of two external resis- inherent in most LDO regulator architectures, see Figure 1. tors as shown in Figure 3. The device servos the output The LTC3026-1 also includes a soft-start feature to prevent to maintain the ADJ pin voltage at 0.4V (referenced to excessive current flow at V ground). Thus, the current in R1 is equal to 0.4V/R1. For IN during start-up. When the LDO is enabled, the soft-start circuitry gradually increases good transient response, stability and accuracy the current the LDO reference voltage from 0V to 0.4V over a period in R1 should be at least 80μA, thus, the value of R1 should of approximately 200μs, see Figure 2. be no greater than 5k. The current in R2 is the current in R1 plus the ADJ pin bias current. Since the ADJ pin bias current is typically <10nA it can be ignored in the output voltage calculation. The output voltage can be calculated using the formula in Figure 3. Note that in shutdown the output is turned off and the divider current will be zero once COUT is discharged. 30261f 8